Occasional Contributor
Occasional ContributorHello.
The design has 65,536 discrete input frequency values, ranging from 50kHz to 450kHz. The ALTPLL minimum input frequency is 5MHz, correct? If so, do any frequency multiplication megafunctions exist (I'm using a Cyclone III device but will upgrade if necessary) to allow for increasing this range so that it's above the 5MHz minimum before being input into an ALTPLL? If not, I'll add a clock multiplier outside the FPGA first and divide by an equal scale in the ALTPLL to restore the 50kHz to 450kHz range.
The goal is to use ALTPLLs (with reconfiguration) to generate six output clocks at specified phases with respect to the input clock. I've found an example in the literature (see Figure 7 attachment) that shows three ROMs being created to allow for selection from one of three different input frequencies. I have 65,536 different input frequencies. Is there a way to achieve this without creating 65,536 ROMs?
Thanks.
Frequent ContributorYes you are right. The minimum freq for PLL refclk in Cyclone III device is 5MHz.
There are methods for PLL reconfiguration:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf
Thanks.
Eng Wei
Occasional ContributorDesign Example 1 in AN507 shows the PLL being reconfigured with one of three .mif files used to select output frequency. Is there a way - other than manually generating 65,536 .mif files - to achieve what I'm looking to do? Thanks.
Frequent ContributorHi @BigSid
You can also reconfigure the PLL according to method 1 in
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf
Thanks.
Eng Wei
