Occasional Contributor
Frequent ContributorYes you are right. The minimum freq for PLL refclk in Cyclone III device is 5MHz.
There are methods for PLL reconfiguration:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf
Thanks.
Eng Wei
Occasional ContributorDesign Example 1 in AN507 shows the PLL being reconfigured with one of three .mif files used to select output frequency. Is there a way - other than manually generating 65,536 .mif files - to achieve what I'm looking to do? Thanks.
Frequent ContributorHi @BigSid
You can also reconfigure the PLL according to method 1 in
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf
Thanks.
Eng Wei
Frequent ContributorHi @BigSid
I am transferring this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
ContributorI have found that the PLL lock range can be as great as 2:1, so you probably don't need 65535 reconfigurations. Maybe only 4-8 are required.
