Forum Discussion
EngWei_O_Intel
Frequent Contributor
4 years agoYes you are right. The minimum freq for PLL refclk in Cyclone III device is 5MHz.
There are methods for PLL reconfiguration:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf
Thanks.
Eng Wei
BigSid
Occasional Contributor
4 years agoDesign Example 1 in AN507 shows the PLL being reconfigured with one of three .mif files used to select output frequency. Is there a way - other than manually generating 65,536 .mif files - to achieve what I'm looking to do? Thanks.