Honored ContributorHi all
I am trying to use the dividers present in altpll but I am not sure as to how I can ensure that the divider outputs will be synchronised. Can someone please give any pointers as to how I can ensure all the outputs of the dividers remain synchronized? Can I use the areset pin for this? Thanks Anant
Honored ContributorWithin a single PLL they automatically are. Across PLLs, when dividing down to a lower frequency, they are not. (E.g. if two PLLs get the same 100MHz clock and they both create a 50MHz clock, they will be 180 degrees out of alignment half the time.) I build a circuit a long time ago to get around this, but it's a bit of pain. Basically you would run the clock at 100MHz and then use the enable in the clkctrl block to disable the clock every other cycle, and the logic would be in sync for each PLL. The output is no longer a 50/50 duty cycle when dividing down by more than 2. Can you give more details on what you're trying to do. Single PLL or multiple? What frequencies in and out?
Honored ContributorThanks Rysc for your explaination.
I am trying to create multiple clocks from a pll. The problem is if I have an input frequency of less than 5 MHz, the plls wont lock. So I need to multiply the input and at the same time divide the output (so that I can ultimately maintain the ratio.) In this case, I am not sure if all clocks being divided as such would remain in sync or not.Honored ContributorAll PLLs multiply up the incoming clock. If you have a 350MHz clock coming in, the VCO still runs at a much faster rate, and might be 2-4x that(depending on device's VCO range and some other factors). So let's say it gets multiplied by 2 to an internally running 700MHz VCO, and the user wants two 350MHz output clocks. Coming from the same PLL, they are automatically aligned. I'm not completely sure of the mechanism, but designs rely on this all the time. Now, starting with a slower clock, you still multiply it up to the VCO range and they should be aligned coming out.
To your point, if the clock is less than 5MHz, how are you planning on multiplying it up to a range that the PLL will lock onto?Honored ContributorHi Rysc
thanks again for your reply. I was intending to multiply the input with a number so that it becomes more than 5. So if suppose the input clock is 3, i would multiply it by two before giving as input. Then I would divide the clock by 2 so that I again get 3 MHz. I figured out a way this could be done (thanks to my manager!!). We have to use altclkctrl for getting the slower clock. So, I would feed my input clock to the pll and get a high frequency clock. Then I would use the altclkctrl for getting the slower clocks. The only trouble I am having here is the violations. I have to see how to remove them.
