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Altera_Forum
Honored Contributor
13 years agoaltpll dividers
Hi all I am trying to use the dividers present in altpll but I am not sure as to how I can ensure that the divider outputs will be synchronised. Can someone please give any pointers as to how I...
Altera_Forum
Honored Contributor
13 years agoHi Rysc
thanks again for your reply. I was intending to multiply the input with a number so that it becomes more than 5. So if suppose the input clock is 3, i would multiply it by two before giving as input. Then I would divide the clock by 2 so that I again get 3 MHz. I figured out a way this could be done (thanks to my manager!!). We have to use altclkctrl for getting the slower clock. So, I would feed my input clock to the pll and get a high frequency clock. Then I would use the altclkctrl for getting the slower clocks. The only trouble I am having here is the violations. I have to see how to remove them.