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Altera_Forum
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13 years ago

altpll dividers

Hi all I am trying to use the dividers present in altpll but I am not sure as to how I can ensure that the divider outputs will be synchronised. Can someone please give any pointers as to how I...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thanks Rysc for your explaination.

I am trying to create multiple clocks from a pll.

The problem is if I have an input frequency of less than 5 MHz, the plls wont lock. So I need to multiply the input and at the same time divide the output (so that I can ultimately maintain the ratio.)

In this case, I am not sure if all clocks being divided as such would remain in sync or not.