altpll dividers

Within a single PLL they automatically are. Across PLLs, when dividing down to a lower frequency, they are not. (E.g. if two PLLs get the same 100MHz clock and they both create a 50MHz clock, they will be 180 degrees out of alignment half the time.) I build a circuit a long time ago to get around this, but it's a bit of pain. Basically you would run the clock at 100MHz and then use the enable in the clkctrl block to disable the clock every other cycle, and the logic would be in sync for each PLL. The output is no longer a 50/50 duty cycle when dividing down by more than 2. Can you give more details on what you're trying to do. Single PLL or multiple? What frequencies in and out?