Honored Contributor
Honored ContributorAll PLLs multiply up the incoming clock. If you have a 350MHz clock coming in, the VCO still runs at a much faster rate, and might be 2-4x that(depending on device's VCO range and some other factors). So let's say it gets multiplied by 2 to an internally running 700MHz VCO, and the user wants two 350MHz output clocks. Coming from the same PLL, they are automatically aligned. I'm not completely sure of the mechanism, but designs rely on this all the time. Now, starting with a slower clock, you still multiply it up to the VCO range and they should be aligned coming out.
To your point, if the clock is less than 5MHz, how are you planning on multiplying it up to a range that the PLL will lock onto?
