Altera Stratix4 GX Dev Kit 530 vs Terasic DE4

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I need some inputs. I am looking for a dev kit of Stratix 4 to interface with wireless RF I/O link, saving to storage through SATA port and getting input from ADC (HSMC) in real time.

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How fast is your ADC? What logic standard does it need to interface to the FPGA? For example, high-speed transceiver, LVDS, or 3.3V I/O?

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Question 1:

I have a question. The Altera one cost about $8000 whereas Terasic's is $3000.

Apart from a few differences in specs, Terasic's one has include more feature such as SATA ports.

Is there any reason?

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The Altera Stratix IV board was available long before the DE4. The differences in the board designs are mainly due to Terasic having more time to think about things. I don't think there were any SATA IP cores initially, so perhaps Altera wasn't thinking about them when they defined their board.

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Question 2:

For DE4, is there any free IPCore (Nios, Sata etc.) included or we have to purchase Quartus II, Modelsim, preferred IP cores seperately? How about Altera dev kit in this case, they included in the bundle which mark up the price?

It is because I can see Altera Dev Kit is not bundle with any other hardware except the main kit only. So perhaps DE4 is a better choice.

Any suggestion?

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Create your system design, and then start comparing features on the two boards. Also look at HSMC daughter cards.

Ultimately price will most likely factor in. If you can get someone to confirm that all the features on the DE4 board work, then you would buy that board.

I have a couple of the Altera Stratix IV GX Development kits. If you have questions regarding a specific interface on that board, I can let you know if I've tested it.

Cheers,

Dave

Good morning all Gurus,

Basically it will be a realtime system running 24/7. I wish to include the following features into stratix 4 V530, wondering whether it has enough LE for that if not all can find in daughter board, such as the RF link.

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Input 1>> 6 channel of 14bits ADC 400 MSa/s, connected through LVDS-HSMC bridge (Texas daughterboards)

Input 2>> timestamp text string from a timing device (RS232 interface)

I/O 1 >> high speed 2.4GHz RF wireless link communication (can't find any daughterboard yet)

I/O 2 >> read/write SATA 3 mechanical harddisk or SSD (will use Terasic Daughter board)

I/O 3 >> Gigs of DDR3 RAM.

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I don't see any GPIO pin for jumper wires (e.g. interrupt). Is there a fan-out board for customised GPIO logics?

I think Terasic-DE4 DDR2 is fast enough to intake ADC streaming. (Terasic says DE4 DDR2 can reach the max of 102Gbps)

14bits * 400MSample/s = 5.6 Gbps, 6 channels in parallel will reach 33.6 Gbps, theoretically. Please correct me if this is incorrect.

Questions:

I know each kit come with 2 HSMC only. Any suggestion to use a Stratix 4 with 6 units of ADC?

Newbie doubts: Do we need to rely on paid-IPcores for the features aforementioned? or we can take time to design every bits in FPGA...

Thanks

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Basically it will be a realtime system running 24/7.

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And you want to build this system out of evaluation boards?

They're not really designed for actual use in real systems. For example, the mechanical interface to the HSMC connectors on the Stratix IV GX board is not really that great. I have Samtec cables connecting the board to other boards, and there is no way of mechanically locking the cables to the board. I suspect you will face the same issue when trying to mechanically stabilize the TI development kits.

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Input 1>> 6 channel of 14bits ADC 400 MSa/s, connected through LVDS-HSMC bridge (Texas daughterboards)

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6 x 14-bits plus clock plus whatever else requires at least 90 LVDS signals (assuming these are all differential). There's only 17 LVDS RX signals and a couple of input clocks defined per HSMC connector, so at best, you will be able to interface to 2 ADCs on the S4GXDK.

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Input 2>> timestamp text string from a timing device (RS232 interface)

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Should be no problem.

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I/O 1 >> high speed 2.4GHz RF wireless link communication (can't find any daughterboard yet)

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Are you interfacing this to the ADCs, or are you looking for a board that performs demodulation and outputs digital data? I don't have any suggestions, I'm just trying to understand the interface requirement.

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I/O 2 >> read/write SATA 3 mechanical harddisk or SSD (will use Terasic Daughter board)

I/O 3 >> Gigs of DDR3 RAM.

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You should be able to test these components in simulation and synthesis without having to buy a board. That will give you an idea of the logic resources required.

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I don't see any GPIO pin for jumper wires (e.g. interrupt). Is there a fan-out board for customised GPIO logics?

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Terasic has an HSMC-to-GPIO board. However, you will be using the HSMC ports for the ADCs ...

There is an LCD header, you can remove the LCD and use that for GPIO.

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I think Terasic-DE4 DDR2 is fast enough to intake ADC streaming. (Terasic says DE4 DDR2 can reach the max of 102Gbps)

14bits * 400MSample/s = 5.6 Gbps, 6 channels in parallel will reach 33.6 Gbps, theoretically. Please correct me if this is incorrect.

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Don't believe marketing. Always simulate.

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I know each kit come with 2 HSMC only. Any suggestion to use a Stratix 4 with 6 units of ADC?

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You first need to figure out whether the final system design will use a custom board. If it does, then use the DE4 or S4GXDK boards to prototype your system with only two ADCs.

If your custom board needs to interface to all 6 ADCs simultaneously, and those ADCs use LVDS, then you will need to check the I/O requirements of the devices you are interested in.

Here's some notes:

http://www.ovro.caltech.edu/~dwh/wbsddc/high_speed_samplers_notes.pdf (http://www.ovro.caltech.edu/%7edwh/wbsddc/high_speed_samplers_notes.pdf)

The Stratix IV GX 530 in the largest package has about 98 receivers. This would likely be just enough to interface to the ADCs.

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Newbie doubts: Do we need to rely on paid-IPcores for the features aforementioned? or we can take time to design every bits in FPGA...

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The DDR3 and SATA IP cores will require licenses. The rest of the IP will need to be developed by you.

Cheers,

Dave

Morning Dave,

Yes, it will be a partially customised board, eventually. For now, no much choice for me because I will need a piece of hardware, i.e. the evaluation board to test on whatever I could have simulated with Modelsim.

Yes, initially I am thinking of doing 1 or 2 ADC per board, and extend it in customised board but that's the story after every feature is completed perfectly on evaluation.

Oh, thanks for the explanation of LVDS and HSMC port. That's really good for me to think further in I/O resources management.

Hm... by assigning unuse transceiver into other ADC modules... since I only need 1 storage... thanks, Dave.

If I am using only ADC in the evaluation for testing, I think the DDR2 should be fast enough for data rate <10Gbps.

For RF link, it is the wireless communicator to send the data file from SATA storage to PC on User's request or 'When' the ADC input meet certain criteria.

In this care, if I cant find any Rf link daughterboard from Altera's partners, what can I do? Because FPGA is solely digital, right?

Otherwise, I believe I can look for some sort of WiFi (free license band) evaluation board from other brand and then code the FPGA to interface correctly with it, by developing the interface logic using GPIO. Do you think this is feasible?

I hope I manage to simulate all the feature correctly in Modelsim, especially the timing... :)

Oh by the way, Dave said SATA3 and DDR3 need IPcore license. How about SATA2 and DDR2, same? Can we simulate these licensed protocol in Modelsim? :(

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Yes, it will be a partially customised board, eventually. For now, no much choice for me because I will need a piece of hardware, i.e. the evaluation board to test on whatever I could have simulated with Modelsim.

Yes, initially I am thinking of doing 1 or 2 ADC per board, and extend it in customised board but that's the story after every feature is completed perfectly on evaluation.

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Ok, that sounds like a reasonable plan.

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If I am using only ADC in the evaluation for testing, I think the DDR2 should be fast enough for data rate <10Gbps.

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What clock rate do you really need to run the ADC at? What is the bandwidth of the signal you are trying to sample? Your ADC could be run at ~400MHz and then the signal down-converted and digitally filtered, so the data rate to DDR would be lower.

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For RF link, it is the wireless communicator to send the data file from SATA storage to PC on User's request or 'When' the ADC input meet certain criteria.

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Why would you want to do this wirelessly? What is wrong with a PCIe link, or a 10GbE link? You'll get much higher bandwidth over wires. You wireless link would not have enough bandwidth to stream the raw ADC data, but it could be used to transmit a 'snapshot'.

To start with, build a system with a PCIe DE4 board, and use a WiFi card controlled by the host computer. That way you can decide whether you really need the WiFi feature or not.

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In this care, if I cant find any Rf link daughterboard from Altera's partners, what can I do? Because FPGA is solely digital, right?

Otherwise, I believe I can look for some sort of WiFi (free license band) evaluation board from other brand and then code the FPGA to interface correctly with it, by developing the interface logic using GPIO. Do you think this is feasible?

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You need to think about the reason for the wireless link a little more. I am sure there are wifi links that you can buy and interface to digitally. I haven't used any, so cannot offer suggestions.

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I hope I manage to simulate all the feature correctly in Modelsim, especially the timing... :)

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Modelsim will tell you the bus bandwidths over the interfaces, eg. what the actual DDR3 bandwidth is. Quartus will tell you what the place-and-route timing is.

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Oh by the way, Dave said SATA3 and DDR3 need IPcore license. How about SATA2 and DDR2, same? Can we simulate these licensed protocol in Modelsim? :(

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You can simulate all of the Altera IP cores without a license. You can test most (all?) of the IP cores as well, they just have a time-limited feature.

Cheers,

Dave

Hi Dave,

Wireless link is really important in my plan because there will be several FPGA systems at remote locations but I am with only single host PC. It is like a 'star network'.

The ADC, RAM and FPGA will be running in realtime but the SATA and wireless link will not streaming in realtime. It will allow the remote user's request to download the ADC sample/snapshot (could be in 10++ MB capacity per text file) from its SATA storage to the host PC at another physical location.

The frequency of my incident signals come from a UltraWideBand receiver, usually at lower MHz band. So basically just stick to the ADC's peak sampling rate of 400MSa/s. If current plan works, I will make another GSa/s system. But this is unimportant for now.

More critical issue is whether I will get the right development board and software.

I feel like go for the Altera kit since Terasic-DE4 will not include the full version license for Quartus2 and Modelsim. The licenses for this software cost another $5000... :)

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Wireless link is really important in my plan because there will be several FPGA systems at remote locations but I am with only single host PC. It is like a 'star network'.

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Ok, that makes sense. However, the wireless link does not have to be part of the FPGA design, it only needs to be part of the node design. If each node is a PC with an FPGA card and a WiFi card plugged into it, then all you need to find is an appropriate WiFi PCIe card, and drivers. Just because an FPGA *could* be used for the WiFi, does not mean it should be. FPGAs are expensive, PCs are cheap, use the PC and as much commercial hardware where you can, and only build custom hardware where you have to.

Does each processing node have to use 6 ADCs?

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The ADC, RAM and FPGA will be running in realtime but the SATA and wireless link will not streaming in realtime. It will allow the remote user's request to download the ADC sample/snapshot (could be in 10++ MB capacity per text file) from its SATA storage to the host PC at another physical location.

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Ok. But don't use a text file, use a binary file, otherwise you are wasting bandwidth :)

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The frequency of my incident signals come from a UltraWideBand receiver, usually at lower MHz band. So basically just stick to the ADC's peak sampling rate of 400MSa/s.

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What are the *exact* frequency requirements of your system? Your system should only store exactly the bandwidth needed for each operating mode.

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If current plan works, I will make another GSa/s system. But this is unimportant for now.

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What sampling frequency and how many bits? National semiconductor has 3GHz clock rate parts, e2v have 5GHz parts, etc.

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More critical issue is whether I will get the right development board and software. I feel like go for the Altera kit since Terasic-DE4 will not include the full version license for Quartus2 and Modelsim. The licenses for this software cost another $5000... :)

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Before buying too many licenses, check that the system design will work correctly.

I suspect you need Quartus to synthesize for the Stratix IV device. I doubt that you need the full edition of Modelsim; try the web edition first.

Cheers,

Dave

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For DE4, is there any free IPCore (Nios, Sata etc.) included or we have to purchase Quartus II, Modelsim, preferred IP cores seperately?

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I don't know of any free SATA IP cores. I know IntelliProp provides SATA cores that work well on the Stratix IV for all possible speeds of SATA. I am biased though since I work for them. If you want to get a datasheet, I have provided a link to the website below.

http://intelliprop.com/products-storage_interface_cores.htm

-Ben

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I don't know of any free SATA IP cores. I know IntelliProp provides SATA cores that work well on the Stratix IV for all possible speeds of SATA. I am biased though since I work for them. If you want to get a datasheet, I have provided a link to the website below.

http://intelliprop.com/products-storage_interface_cores.htm

-Ben

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Thanks Ben, may I know what is SATA host and SATA device?

Is it like USB standard, which has host and client too...?

If I am using SATA3 as a storage device in FPGA system, is it a 'device'?