Altera Stratix4 GX Dev Kit 530 vs Terasic DE4

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Sorry I am not fully understand this. The timestamps come in a combination of Alphabets and Numbers. I thought ASCII has the least bits to represent them. How do they occupies less BW if using binary form? for example, "A" and "3" are decimal 63 and 51 in ASCII table. They are in text form when being sent to FPGA. Then what should I print in the storage device to save bandwidth?

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Time stamps do not have to be ASCII. You can store an accurate timestamp using a single 32-bit integer, and an even more accurate timestamp using a 64-bit integer.

For example, in some of my designs I have version and timestamp generics that get passed down to read-only status registers. Software can then report the hardware version, and its build timestamp.

Using the Cygwin/Linux date command you can get:

#  Build timestamp
set timestamp 

or in pure Tcl

#  Build timestamp#   - Tcl  returns the same as 
set timestamp 

Read the Linux man pages or the Tcl pages for the formatting, and commands to convert the 32-bit value back into a timestamp string.

Your binary data format should have a definition document. The format might be something like:

1) Endian flag

2) 32-bit timestamp

3) Sampling frequency

4) Sample bit width

5) Number of samples

6) Sample data

If you do not put an endian flag in the data format, then you must define the binary data format as big-endian-only or little-endian-only. So that different machine architectures will know how to read the binary files.

I use CORBA Common Data Representation (CDR) for my binary data formats. The ACE C++ library has stream encode and decode functions. The binary data format is used for passing data between clients and servers, and for writing binary data files.

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Oh, now I get it. However, I do not use a filter. I am sampling the raw analog into FPGA to analyse the voltage level of sampled pulses, regardless to what the source is streaming. I should say it at the beginning that my system is not Audio/Video system. It is a monitoring system which will sample whatever kind of random noise/transients waveforms or pulses from a constant low frequency line. This is the reason I will shift to higher ADC frequency incrementally after the first design.

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You need to check what the signal looks like with a wide bandwidth oscilloscope or spectrum analyzer. Your ADC may have a wider input bandwidth than your sampling rate, and if it does, then signal will alias into the digital baseband produced by the ADC. This may corrupt your results.

If you are only interested in signals up to 200MHz (for a 400MHz clock rate), then you should really have a 200MHz low-pass filter.

Cheers,

Dave

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If you store a 32-bit hex value as the 8 ASCII characters "12345678", it uses more bits than storing the binary data directly. Each ASCII character requires 8-bits to represent, whereas the character represents only 4-bits of the number you are storing.

The binary file will be half the size of an ASCII file.

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Sorry I am not fully understand this. The timestamps come in a combination of Alphabets and Numbers. I thought ASCII has the least bits to represent them. How do they occupies less BW if using binary form? for example, "A" and "3" are decimal 63 and 51 in ASCII table. They are in text form when being sent to FPGA. Then what should I print in the storage device to save bandwidth?

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I understand, but my question was what is the exact bandwidth you are sampling.

If you are sampling a signal at 400MHz, you will have to filter it first with analog filters. Its unlikely you can get extremely sharp analog filters, so you will sample some bandwidth that is aliased, or has low signal. This part of the bandwidth can be digitally filtered, and the signal can then be re-sampled to a lower data rate. The re-sampled data can then be stored. This will save you bandwidth.

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Oh, now I get it. However, I do not use a filter. I am sampling the raw analog into FPGA to analyse the voltage level of sampled pulses, regardless to what the source is streaming. I should say it at the beginning that my system is not Audio/Video system. It is a monitoring system which will sample whatever kind of random noise/transients waveforms or pulses from a constant low frequency line. This is the reason I will shift to higher ADC frequency incrementally after the first design.

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Altera provides simulation versions of their IP. If you can get Modelsim working for your design, then you need to synthesize and check that the device has enough logic and can meet timing. I'd recommend incrementally testing (simulate plus synthesize) each interface, and obtain a logic estimate at each stage. Then as you start to integrate the system, you will have an expectation of logic usage. If each subsystem meets timing, then the whole system should meet timing too.

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This is exactly what I have in mind but unsure. With your words, now it is confirmed. hooray~

Rgds,

Wai Siang

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origianlly the timestamp is in ASCII. How do we save in binary bits that occupies less bandwidth?

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If you store a 32-bit hex value as the 8 ASCII characters "12345678", it uses more bits than storing the binary data directly. Each ASCII character requires 8-bits to represent, whereas the character represents only 4-bits of the number you are storing.

The binary file will be half the size of an ASCII file.

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There are 3 operating mode in my design plan.

The ADC input is 400MSa/s. The FPGA route the sample to the DDR3 in realtime.

Then write to SATA HDD in max speed that the HDD supports (apparently it is at data rate of SATA2/3).

User may request remote download through wireless link, then FPGA will read from SATA and send over the wireless module (wireless eva kit is usually at USB rate).

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I understand, but my question was what is the exact bandwidth you are sampling.

If you are sampling a signal at 400MHz, you will have to filter it first with analog filters. Its unlikely you can get extremely sharp analog filters, so you will sample some bandwidth that is aliased, or has low signal. This part of the bandwidth can be digitally filtered, and the signal can then be re-sampled to a lower data rate. The re-sampled data can then be stored. This will save you bandwidth.

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The system has different features integrated altogether in an FPGA. It may not synthesizable even it is working in ModelSim.

Isnt Quartus 2 only works with hardware?

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Altera provides simulation versions of their IP. If you can get Modelsim working for your design, then you need to synthesize and check that the device has enough logic and can meet timing. I'd recommend incrementally testing (simulate plus synthesize) each interface, and obtain a logic estimate at each stage. Then as you start to integrate the system, you will have an expectation of logic usage. If each subsystem meets timing, then the whole system should meet timing too.

Cheers,

Dave

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Did You install the license server after modelsim installation?

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License Server? Is that another software installer?

I only install "11.0_modelsim_ae_windows.exe" and "11.0sp1_modelsim_ae_windows.exe".

Then I create 2 env variables.

So I need a License Server installer from Altera?

My license link looks like this "[email protected]"

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Probably web edition won't support Stratix devices and You'll need subscription edition.

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Yes, thank you. My place got the network license for full edition Modelsim too. But my Local Machine seems cant get through when running the ModelSim 6.6d. It always pop up an error message regarding MGSL_LICENSE_FILE and and LM_LICENSE_FILE. Then asking me to use the 'lmulti lmdiag' but I failed to find this exe.

I did setup the environment after this but still not working. I wonder what's wrong to my environment variable and I do not know where to get help on this issue.

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Ok, that makes sense. However, the wireless link does not have to be part of the FPGA design, it only needs to be part of the node design. If each node is a PC with an FPGA card and a WiFi card plugged into it, then all you need to find is an appropriate WiFi PCIe card, and drivers. Just because an FPGA *could* be used for the WiFi, does not mean it should be. FPGAs are expensive, PCs are cheap, use the PC and as much commercial hardware where you can, and only build custom hardware where you have to.

Does each processing node have to use 6 ADCs?

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Initially I will experiment only an ADC with a Dev Kit. There will be 6 ADC channels at maximum in final customised board, by reassigning the transceiver as you suggested.

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Ok. But don't use a text file, use a binary file, otherwise you are wasting bandwidth :)

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Agree. origianlly the timestamp is in ASCII. How do we save in binary bits that occupies less bandwidth?

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What are the *exact* frequency requirements of your system? Your system should only store exactly the bandwidth needed for each operating mode.

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There are 3 operating mode in my design plan.

The ADC input is 400MSa/s. The FPGA route the sample to the DDR3 in realtime.

Then write to SATA HDD in max speed that the HDD supports (apparently it is at data rate of SATA2/3).

User may request remote download through wireless link, then FPGA will read from SATA and send over the wireless module (wireless eva kit is usually at USB rate).

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What sampling frequency and how many bits? National semiconductor has 3GHz clock rate parts, e2v have 5GHz parts, etc.

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14bits and 400MSamples per second at my first wishlist. So 5.6Gbps in total.

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Before buying too many licenses, check that the system design will work correctly.

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If Stratix 4 has been proven to drive the features aforementioned (i.e. digital interfaces), is it possible that the system design will still fail? It worries me .

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I suspect you need Quartus to synthesize for the Stratix IV device. I doubt that you need the full edition of Modelsim; try the web edition first.

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Yes, agree. The system has different features integrated altogether in an FPGA. It may not synthesizable even it is working in ModelSim.

Isnt Quartus 2 only works with hardware?

Rgds,

WaiSiang