Honored Contributor
Honored ContributorMorning Dave,
Yes, it will be a partially customised board, eventually. For now, no much choice for me because I will need a piece of hardware, i.e. the evaluation board to test on whatever I could have simulated with Modelsim. Yes, initially I am thinking of doing 1 or 2 ADC per board, and extend it in customised board but that's the story after every feature is completed perfectly on evaluation. Oh, thanks for the explanation of LVDS and HSMC port. That's really good for me to think further in I/O resources management. Hm... by assigning unuse transceiver into other ADC modules... since I only need 1 storage... thanks, Dave. If I am using only ADC in the evaluation for testing, I think the DDR2 should be fast enough for data rate <10Gbps. For RF link, it is the wireless communicator to send the data file from SATA storage to PC on User's request or 'When' the ADC input meet certain criteria. In this care, if I cant find any Rf link daughterboard from Altera's partners, what can I do? Because FPGA is solely digital, right? Otherwise, I believe I can look for some sort of WiFi (free license band) evaluation board from other brand and then code the FPGA to interface correctly with it, by developing the interface logic using GPIO. Do you think this is feasible? I hope I manage to simulate all the feature correctly in Modelsim, especially the timing... :) Oh by the way, Dave said SATA3 and DDR3 need IPcore license. How about SATA2 and DDR2, same? Can we simulate these licensed protocol in Modelsim? :(
