--- Quote Start ---
Yes, it will be a partially customised board, eventually. For now, no much choice for me because I will need a piece of hardware, i.e. the evaluation board to test on whatever I could have simulated with Modelsim.
Yes, initially I am thinking of doing 1 or 2 ADC per board, and extend it in customised board but that's the story after every feature is completed perfectly on evaluation.
--- Quote End ---
Ok, that sounds like a reasonable plan.
--- Quote Start ---
If I am using only ADC in the evaluation for testing, I think the DDR2 should be fast enough for data rate <10Gbps.
--- Quote End ---
What clock rate do you really need to run the ADC at? What is the bandwidth of the signal you are trying to sample? Your ADC could be run at ~400MHz and then the signal down-converted and digitally filtered, so the data rate to DDR would be lower.
--- Quote Start ---
For RF link, it is the wireless communicator to send the data file from SATA storage to PC on User's request or 'When' the ADC input meet certain criteria.
--- Quote End ---
Why would you want to do this wirelessly? What is wrong with a PCIe link, or a 10GbE link? You'll get much higher bandwidth over wires. You wireless link would not have enough bandwidth to stream the raw ADC data, but it could be used to transmit a 'snapshot'.
To start with, build a system with a PCIe DE4 board, and use a WiFi card controlled by the host computer. That way you can decide whether you really need the WiFi feature or not.
--- Quote Start ---
In this care, if I cant find any Rf link daughterboard from Altera's partners, what can I do? Because FPGA is solely digital, right?
Otherwise, I believe I can look for some sort of WiFi (free license band) evaluation board from other brand and then code the FPGA to interface correctly with it, by developing the interface logic using GPIO. Do you think this is feasible?
--- Quote End ---
You need to think about the reason for the wireless link a little more. I am sure there are wifi links that you can buy and interface to digitally. I haven't used any, so cannot offer suggestions.
--- Quote Start ---
I hope I manage to simulate all the feature correctly in Modelsim, especially the timing... :)
--- Quote End ---
Modelsim will tell you the bus bandwidths over the interfaces, eg. what the actual DDR3 bandwidth is. Quartus will tell you what the place-and-route timing is.
--- Quote Start ---
Oh by the way, Dave said SATA3 and DDR3 need IPcore license. How about SATA2 and DDR2, same? Can we simulate these licensed protocol in Modelsim? :(
--- Quote End ---
You can simulate all of the Altera IP cores without a license. You can test most (all?) of the IP cores as well, they just have a time-limited feature.
Cheers,
Dave
Honored Contributor
