Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

OPN:DK-DEV-AGI027RES (Power Solution 1)
SN: AGIPCIE8000296

1.Failure Symptom
The CXL device fails to enumerate when using the CXL Type-3 IP design example.
•    lspci -vvv | grep 0ddb does not detect the CXL device
•    numactl -H does not report a CXL NUMA node
The issue persists across multiple system reboots and bitstream rebuilds. A factory reset was attempted but did not resolve the issue.

2. When did the failure happen? When did you buy the part, and when did you receive it?
The device was received approximately two years ago.
The failure was observed during initial bring-up and has been present since first use

3. How did you discover the failure? Please describe it in detail.
We programmed the FPGA with the CXL Type-3 design example; however, the host server failed to enumerate the device.
The same bitstream works correctly on other Agilex FPGA boards, indicating the issue is specific to this unit

4. In which part of your process did you find the issue (Lab, production, quality, etc.)?
Lab environment.
4.1 Was the device already in the field? How many times has it been used?
No. The device has only been used in a controlled lab environment for bring-up and testing

5. How many units failed and how many units were used/tested by you? Which is the production code?
•    Failed units: 1
•    Units tested: Multiple Agilex FPGA boards
•    Production code: Not available
Only this unit exhibits the failure.

6. How did you determine the failure? Please elaborate on the procedures.
Multiple bring-up attempts were performed using known-good hardware, software, and bitstreams.
•    6.1 Internal Debug: No internal physical failure analysis (e.g., X-ray or short-circuit testing) was performed.
•    6.2 Device Swap: Yes. Replacing the board with a known-good FPGA resolves the issue.

7. Was the failing unit ever working before the failure?
No. The unit has never functioned correctly since initial use.

8. How did you rule out electrical overstress (EOS) or electrostatic discharge (ESD)?
There is no visible physical damage on the FPGA or PCB.
The board has been handled according to standard ESD-safe lab procedures.

9. What are your expectations from this failure analysis?
Identify the root cause of the failure and either restore proper CXL IP functionality or provide a replacement device

10. Have you re-balled your device? If yes, was it lead-free reballing?
No. The device has not been re-balled, and no third-party rework has been performed.

11. Please add pictures of the device from the top and the bottom.See attached. 

12. Is there any other relevant information that could assist in the failure analysis?
No additional information at this time.