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nskim's avatar
nskim
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1 month ago

Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

OPN:DK-DEV-AGI027RES (Power Solution 1) SN: AGIPCIE8000296 1.Failure Symptom The CXL device fails to enumerate when using the CXL Type-3 IP design example. •    lspci -vvv | grep 0ddb does not ...
Programmable Logic Device
quality|reliability
nskim's avatar
nskim
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1 month ago

Hi Rong,

We have tried Quartus Pro 24.3 and 24.1, both newer than 23.4. The CXL design example fails to bring up the device on both Quartus versions.

RongY_altera's avatar
RongY_altera
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1 month ago

You may need to put two DDR4-2666 DIMM memory onto the dev kit.

 

Regards,

Rong

 

  • nskim's avatar
    nskim
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    1 month ago

    Hi Rong,

    We programmed the same bitstream onto another FPGA in our lab, and it works correctly on that device. Based on our understanding, the Agilex 7 I-series card already has 16 GB of on-card DRAM, and the CXL design example is expected to work with this configuration. In addition, we also tested a PCIe IP configuration that does not require external memory, but it failed as well.

    Please let us know if installing the two DDR4-2666 DIMMs is still required in this case.