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YorkChang's avatar
YorkChang
Icon for New Contributor rankNew Contributor
2 days ago

Agilex 7 (F-tile/R-tile) PCIe Gen5 RX Compliance Test Issue -some lanes can't enter Loopback

Hi Teams, We are currently working on a custom PCIe Add-in Card based on Agilex 7 (F-tile / R-tile). Note that the FPGA firmware is provided to us by our end customer. Design Context: According to ...
Core Logic
Programmable Logic Device
quality|reliability
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 hours ago

Hi YorkChang 

As discussed, we will continue the discussion of this issue through the APS case, I will now transition this thread to the community. If you have any new questions, please feel free to open a new thread and the Altera experts will be happy to assist.

Thanks. 
Best Regards, 
Ven