New ContributorHello
It's unclear for me about how to use IO LANE with SERDES functionality.
Regular Contributor
Super ContributorHi,
I didn't yet start designing with Agilex FPGA, just have Arrow AXE5000 Development Kit for evaluation purposes. Thus I can't answer your question from own experience.
You are quoting Agilex 5 General-Purpose I/O User Guide, 2.1. HSIO Bank Overview. I also read the description so that an I/O lane can be either used for SERDES RX or TX. But as a the title says, it's only an overview.
For detailed specification of differential pin constraints you should refer to Agilex 5 LVDS SERDES User Guide. There are e.g. complex rules for sharing I/O banks between single-ended and differential pins. Finally, it's most likely simpler to evaluate the feasibility of a specific pin assignment in Quartus.
Regards
Frank
