Hello,Using a PCIe IP in Root Port on a AGILEX 5, I have to use the GTS Reset Sequencer Intel FPGA IP configured in PCIe.With Quartus 2025.1, the i_refclk_bus_out port appears on the GTS Reset Sequencer Intel FPGA IP.There is no port on the PCIe IP to connect to port i_refclk_bus_out.So, to which signal or to what value the port i_refclk_bus_out must be connected ?Thanks.Serge

Hi ,The i_refclk_bus_out is an input signal/reference clock who indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.If refer to https://www.intel.com/content/www/us/en/docs/programmable/813966/25-1/reset-signals.htmlIF this is something that will causing the compilation to be fail, you may connect something call "refclk_bus_out" from non PCIe IP to the GTS Reset Sequence IP.Regards,Wincent

Hello Wincent,Thank you for your answer.To be accurate, I can leave the port input i_refclk_bus_out floating without setting it to 0 or to 1, correct ?Thanks.Serge

Hi Serge,Theoretically Yes, as mentioned the clock is use for indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.If there is no anything to monitor , you can let it be floated, I never try this implementation before.In cases the compilation is fail, please connected to any other IP who contain "refclk_bus_out/any similar" Regards,Wincent_Altera

Hello Wincent,I do not have any other IP in my Platform Designer which contains any "refclk_bus_out/any similar".So I wanted to know at which value should I set it, 0 or 1 ?To make everything ok.I did not find any information about that. Thank you.Serge

Hi Serge,If you does not have the PHY IP inside your design, please set it as "0".I try it in a simple design , I seeing the compilation passing, please have a try in rootport as well.IF you seeing any new issue , please let me know the error code or any printscreen will do. We can solve this together.Regards,Wincent_Altera

Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?

33 Replies

Wincent_Altera
Regular Contributor
6 months ago
Hi ,

The i_refclk_bus_out is an input signal/reference clock who indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.
If refer to https://www.intel.com/content/www/us/en/docs/programmable/813966/25-1/reset-signals.html
IF this is something that will causing the compilation to be fail, you may connect something call "refclk_bus_out" from non PCIe IP to the GTS Reset Sequence IP.

Regards,
Wincent
- Serge93
  Occasional Contributor
  6 months ago
  Hello Wincent,
  Thank you for your answer.
  To be accurate, I can leave the port input i_refclk_bus_out floating without setting it to 0 or to 1, correct ?
  Thanks.
  Serge
  - Wincent_Altera
    Regular Contributor
    6 months ago
    Hi Serge,
    
    Theoretically Yes, as mentioned the clock is use for indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.
    If there is no anything to monitor , you can let it be floated, I never try this implementation before.
    In cases the compilation is fail, please connected to any other IP who contain "refclk_bus_out/any similar"
    
    Regards,
    Wincent_Altera
Wincent_Altera
Regular Contributor
6 months ago
Hi Serge,

Are you able to try on yourside ?

Regards,
Wincent
Wincent_Altera
Regular Contributor
6 months ago
Hi,
Let me know if you need more time to response to this cases.
Regards
Wincent_Altera
- Serge93
  Occasional Contributor
  6 months ago
  Hello Wincent,
  Monday was off in France.
  I could not answer to you because Quartus failed with the following error message :
  Quartus 2025.1 fails when using the PCIe IP (GTS AXI Streaming IP) :
  Error(24542): VHDL error at gts_axi_streaming.vhd(2001): expression has 20 elements; expected 22
  I have a project test case to reproduce the problem.
  Are you able to work on this problem ?
  Thnaks.
  Serge
  - Wincent_Altera
    Regular Contributor
    6 months ago
    Hi Serge,
    
    Is it possible to attach the design .qar file here ?
    Let me check if I can help to resolve this or not.
    
    Regards,
    Wincent
Wincent_Altera
Regular Contributor
5 months ago
Hi Serge,

Is there anything else you think I could provide in this forum thread ?

Regards,
Wincent_Altera
Serge93
Occasional Contributor
5 months ago
Hello Wincent,
Not for the moment, I am still busy with AGILEX 7-I-R-Tile.
I will come back to you afterwards.
Thnak you.
Serge
- Wincent_Altera
  Regular Contributor
  5 months ago
  Hi Serge,
  
  Do you foresee you will take more time to work back on this ?
  IF yes, can I get your help to file a new thread in future when you work back on Agilex5 project ?
  Because if the forum keep idling for too long, I will not longer receive any notification on that, it will get me to lost trace the record.
  
  Please be understand that we are in full commitment to ensure your success.
  
  Regards,
  Wincent
  - Serge93
    Occasional Contributor
    5 months ago
    Hello Wincent,
    Yes it takes longuer than expected on AGILEX 7, so please close this case and I will come back to you when ready on AGILEX 5.
    Thank you for your help.
    Serge

Forum Discussion

Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?

33 Replies

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