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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?

Hello, Using a PCIe IP in Root Port on a AGILEX 5, I have to use the GTS Reset Sequencer Intel FPGA IP configured in PCIe. With Quartus 2025.1, the i_refclk_bus_out port appears on the GTS Reset Se...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi,

Let me know if you need more time to response to this cases.

Regards

Wincent_Altera

  • Serge93's avatar
    Serge93
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Hello Wincent,

    Monday was off in France.

    I could not answer to you because Quartus failed with the following error message :

    Quartus 2025.1 fails when using the PCIe IP (GTS AXI Streaming IP) :

        Error(24542): VHDL error at gts_axi_streaming.vhd(2001): expression has 20 elements; expected 22

    I have a project test case to reproduce the problem.

    Are you able to work on this problem ?

    Thnaks.

    Serge

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      6 months ago

      Hi Serge,

      Is it possible to attach the design .qar file here ?
      Let me check if I can help to resolve this or not.

      Regards,

      Wincent

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        6 months ago

        Hi @Serge93 ,

        Below is my design for i_refclk_bus_out clock - ON the GTS Reset Sequencer Intel FPGA IP

        the compilation pass as well

        I attach the design .qar file here, please have a look.

        Let me know if I could better assist you in anyway. Hope we can solved this.

        Regards,
        Wincent