Serge93
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Re: JTAG Chain Broken on Agilex 7-I Dev Kit
Hello Fakhul, So, About (1) : Yes it is the first time, the board was working well for several months, and one day when I was debugging a new IP, I did several power cycle, and suddenly I could not configure the board, it was amazing. About (2) : My serial number is 8100650, so DK-DEV-AGI027-RA and AGIB027R29A1E1VB About (3) : Please see the picture attached About (4) : I was unable to find you 'Device info -> Read Device Info' menu, where it is ? About (5) : I using the board only in 'Bench Power Mode'. So no, LED D6 is off. Thank you for help. SergeRe: JTAG Chain Broken on Agilex 7-I Dev Kit
Hello Fakhul, So, About (1) : I have set all the switches as asked, please see the picture attached. About (2) : Unfortunately The LED D6 is Off. About (3) : See the picture attached, I cannot communicate with the board, So I cannot get any voltage value. About (4) : Please see the attached picture. About (5): I had to use the J10 instead of J8 to be able to reconfigure the MAX10, otherwise I cannot get the JTAG chain and so I cannot configure the MAX10. I power cycle and the JTAG is still the same... Thank you for your help. SergeRe: JTAG Chain Broken on Agilex 7-I Dev Kit
Hello Fakhul, I already did all what you said including trying to access the board through the BTS. I was able to reconfigure the MAX10 by bypassing the FPGA but it changed nothing. The Agilex 7i is impossible to configure even with an external USB Blaster with reduced clock. kit ordering code : AGIPCIe8100650 / N24193-001 The Result of jtagconfig --debug is : [niosv-shell] C:\Users\serge\AppData\Local\quartus> jtagconfig --debug 1) AGI FPGA Development Kit [USB-1] (JTAG Server Version 25.3.1 Build 100 12/19/2025 SC Pro Edition) Unable to read device chain - JTAG chain broken Captured DR after reset = () Captured IR after reset = () Captured Bypass after reset = () Captured Bypass chain = () JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0 JTAG clock speed 24 MHz Thanks for help. SergeRe: PCIe reset stuck on Arrow Eagle board
Hello Rong, On the Arrow Eagle board : The PIN_CF132 (PCIE_PIN_PERST_N in GTS PCIe IP) is connected to the PERST# pin of the PCIe edge. The PIN_BU109 (PCIE_PIN_PERST_N_I in GTS PCIe IP) is left floating. I do not understand clearly what you mean by "You may check the remaining PERST pins on these two banks." Please see attached the schematic of the Bank 5A and 5B : Please let me know what I have to check exactly. Thanks. SergePCIe reset stuck on Arrow Eagle board
I am doing an NVME Host IP to drive SSD NVME. I'm using an Arrow Agilex-5 EAGLE Board with Device A5ED065BB32AE4SR0 with Q25.1.1 I have connected on the PCIe Edge the AB19-M2PCI board on which I have connected an SSD. The GTS AXI Streaming Intel FPGA IP for PCI Express stay always in reset. The signal 'p0_pin_perst_n' of the GTS AXI Streaming Intel FPGA IP stay at 0. I have connected the following pins : - input p0_pin_perst_n_i_reset_n assigned to PIN_CF132 which is PCIE_RTSb - input p0_pin_perst_n_1_i_reset_n I've tried to assign to many different pins which were reasonable to connect, but was getting error during the Fitting stage. The only pin assignment which passing compilation is suggested by tool: PIN_BU109 which is according to schematics CX_SMB_SDA set_location_assignment PIN_CF132 -to PCIE_PIN_PERST_N set_location_assignment PIN_BU109 -to PCIE_PIN_PERST_N_I # set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to PCIE_PIN_PERST_N -entity top_nvme set_instance_assignment -name WEAK_PULL_DOWN_RESISTOR ON -to PCIE_PIN_PERST_N -entity top_nvme # set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to PCIE_PIN_PERST_N_I -entity top_nvme set_instance_assignment -name WEAK_PULL_DOWN_RESISTOR ON -to PCIE_PIN_PERST_N_I -entity top_nvme Do you have an idea why the GTS AXI Streaming Intel FPGA IP stay at 0 ?
