Serge93
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Re: PCIe reset stuck on Arrow Eagle board
Hello Rong, On the Arrow Eagle board : The PIN_CF132 (PCIE_PIN_PERST_N in GTS PCIe IP) is connected to the PERST# pin of the PCIe edge. The PIN_BU109 (PCIE_PIN_PERST_N_I in GTS PCIe IP) is left floating. I do not understand clearly what you mean by "You may check the remaining PERST pins on these two banks." Please see attached the schematic of the Bank 5A and 5B : Please let me know what I have to check exactly. Thanks. SergePCIe reset stuck on Arrow Eagle board
I am doing an NVME Host IP to drive SSD NVME. I'm using an Arrow Agilex-5 EAGLE Board with Device A5ED065BB32AE4SR0 with Q25.1.1 I have connected on the PCIe Edge the AB19-M2PCI board on which I have connected an SSD. The GTS AXI Streaming Intel FPGA IP for PCI Express stay always in reset. The signal 'p0_pin_perst_n' of the GTS AXI Streaming Intel FPGA IP stay at 0. I have connected the following pins : - input p0_pin_perst_n_i_reset_n assigned to PIN_CF132 which is PCIE_RTSb - input p0_pin_perst_n_1_i_reset_n I've tried to assign to many different pins which were reasonable to connect, but was getting error during the Fitting stage. The only pin assignment which passing compilation is suggested by tool: PIN_BU109 which is according to schematics CX_SMB_SDA set_location_assignment PIN_CF132 -to PCIE_PIN_PERST_N set_location_assignment PIN_BU109 -to PCIE_PIN_PERST_N_I # set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to PCIE_PIN_PERST_N -entity top_nvme set_instance_assignment -name WEAK_PULL_DOWN_RESISTOR ON -to PCIE_PIN_PERST_N -entity top_nvme # set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to PCIE_PIN_PERST_N_I -entity top_nvme set_instance_assignment -name WEAK_PULL_DOWN_RESISTOR ON -to PCIE_PIN_PERST_N_I -entity top_nvme Do you have an idea why the GTS AXI Streaming Intel FPGA IP stay at 0 ?Re: Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?
Hello Wincent, So, I sent you my design which is done without qsys, only with VHDL files. I did not sent you the design from https://github.com/altera-fpga/agilex5-ed-pcie-rp/releases/tag/25.1-1 project and on which I removed nearly everything becasue this is non sens. So, the idea is the Altera IP expert analyze my design to see what is missing to avoid the bus error. >> is the design work well ONLY with GTS Reset sequence and the PCIe IP ? >> I think you might need to connect with the rest right ? I do not understand this questions. The goal is to provide me an instanciation of a GTS AXI Streaming PCIe IP on AGILEX 5 I can compile without errors. Yes we can organize a Team call, I am based in Paris, France. I am available Thursday an Friday morning of this week. Please send me a link. Thanks for help. Serge
