JTAG Chain Broken on Agilex 7-I Dev Kit

Hi Serge,

Thanks for the update. Could you try below:

1. Return all switches to Default Settings. Include: SW2[1:3] = OFF/OFF/OFF (JTAG mode), SW5.1 = OFF (on‑board Download Cable), SW5.2 = OFF (FPGA in chain), SW5.3 = ON (MAX 10 JTAG enabled). If your board uses SW8 instead of SW5, use the equivalent entries in the same table. Refer: Default Settings tables.
2. Check the D6 Power Good LED. Blue ON means all rails are good. If OFF, address power first. Refer: LEDs table. 
3. In BTS, open Power Monitor GUI and capture the rail status screenshot. Refer: “Monitor On‑board Power through Power Monitor GUI.” 
4. In Quartus Programmer, run JTAG Chain Debugger and share the integrity report if auto‑detect still fails. Intel help recommends this when the chain cannot be scanned.
5. Perform Board Restore through Quartus Prime Programmer, then power cycle and retry JTAG. Refer: “Perform Board Restore through Quartus Prime Programmer.” 

You may refer to this user guide for the above steps: Agilex™ 7 FPGA I-Series Development Kit User Guide

If the chain is still broken with the FPGA in the path after the above, it suggests a board‑side JTAG issue, it can indicate a board integrity problem once power and connections are confirmed. We can proceed with RMA.

Please also share clear photos or a list of the current SW1–SW6/SW8 positions.
 

Regards,
Fakhrul