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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

PCIe reset stuck on Arrow Eagle board

I am doing an NVME Host IP to drive SSD NVME.

I'm using an Arrow Agilex-5 EAGLE Board with Device A5ED065BB32AE4SR0 with Q25.1.1

I have connected on the PCIe Edge the AB19-M2PCI board on which I have connected an SSD.

The GTS AXI Streaming Intel FPGA IP for PCI Express stay always in reset.

The signal 'p0_pin_perst_n' of the GTS AXI Streaming Intel FPGA IP stay at 0.

I have connected the following pins :

- input p0_pin_perst_n_i_reset_n assigned to PIN_CF132 which is PCIE_RTSb

- input p0_pin_perst_n_1_i_reset_n I've tried to assign to many different pins which were reasonable to connect, but was getting error during the Fitting stage. The only pin assignment which passing compilation is suggested by tool: PIN_BU109 which is according to schematics CX_SMB_SDA

set_location_assignment PIN_CF132 -to PCIE_PIN_PERST_N
set_location_assignment PIN_BU109 -to PCIE_PIN_PERST_N_I
#
set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to PCIE_PIN_PERST_N -entity top_nvme
set_instance_assignment -name WEAK_PULL_DOWN_RESISTOR ON -to PCIE_PIN_PERST_N -entity top_nvme
#
set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to PCIE_PIN_PERST_N_I -entity top_nvme
set_instance_assignment -name WEAK_PULL_DOWN_RESISTOR ON -to PCIE_PIN_PERST_N_I -entity top_nvme

Do you have an idea why the GTS AXI Streaming Intel FPGA IP stay at 0 ?

2 Replies

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    3 months ago

    Hi,

    According to the pin connection guide, the unused PERST pin for the same GTS bank must be left floating.

    Your PIN_CF132 and PIN_BU109 are on bank 5A and 5B, respectively. You may check the remaining PERST pins on these two banks.


    Regards,

    Rong


    • Serge93's avatar
      Serge93
      Icon for Occasional Contributor rankOccasional Contributor
      3 months ago

      Hello Rong,

      On the Arrow Eagle board :

      The PIN_CF132 (PCIE_PIN_PERST_N in GTS PCIe IP) is connected to the PERST# pin of the PCIe edge.

      The PIN_BU109 (PCIE_PIN_PERST_N_I in GTS PCIe IP) is left floating.

      I do not understand clearly what you mean by "You may check the remaining PERST pins on these two banks."

      Please see attached the schematic of the Bank 5A and 5B :

      Please let me know what I have to check exactly.

      Thanks.
      Serge