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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?

Hello, Using a PCIe IP in Root Port on a AGILEX 5, I have to use the GTS Reset Sequencer Intel FPGA IP configured in PCIe. With Quartus 2025.1, the i_refclk_bus_out port appears on the GTS Reset Se...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Serge,

Do you foresee you will take more time to work back on this ?
IF yes, can I get your help to file a new thread in future when you work back on Agilex5 project ?
Because if the forum keep idling for too long, I will not longer receive any notification on that, it will get me to lost trace the record.

Please be understand that we are in full commitment to ensure your success.

Regards,
Wincent

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hello Wincent,

Yes it takes longuer than expected on AGILEX 7, so please close this case and I will come back to you when ready on AGILEX 5.

Thank you for your help.

Serge

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Serge,

    Thanks for your reply, Looking forward to hear back from you later.

    Regards,

    Wincent