Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?

Hi ,

The i_refclk_bus_out is an input signal/reference clock who indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.

If refer to https://www.intel.com/content/www/us/en/docs/programmable/813966/25-1/reset-signals.html

IF this is something that will causing the compilation to be fail, you may connect something call "refclk_bus_out" from non PCIe IP to the GTS Reset Sequence IP.

Regards,

Wincent