Occasional Contributor
Regular ContributorHi ,
The i_refclk_bus_out is an input signal/reference clock who indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.
If refer to https://www.intel.com/content/www/us/en/docs/programmable/813966/25-1/reset-signals.html
IF this is something that will causing the compilation to be fail, you may connect something call "refclk_bus_out" from non PCIe IP to the GTS Reset Sequence IP.
Regards,
Wincent
Occasional ContributorHello Wincent,
Thank you for your answer.
To be accurate, I can leave the port input i_refclk_bus_out floating without setting it to 0 or to 1, correct ?
Thanks.
Serge
Regular ContributorHi Serge,
Theoretically Yes, as mentioned the clock is use for indicate the fail status signal from GTS PMA/FEC direct PHY FPGA IP or for other IP exclude PCIe IP.
If there is no anything to monitor , you can let it be floated, I never try this implementation before.
In cases the compilation is fail, please connected to any other IP who contain "refclk_bus_out/any similar"
Regards,
Wincent_Altera
Occasional ContributorHello Wincent,
I do not have any other IP in my Platform Designer which contains any "refclk_bus_out/any similar".
So I wanted to know at which value should I set it, 0 or 1 ?
To make everything ok.
I did not find any information about that.
Thank you.
Serge
Regular ContributorHi Serge,
If you does not have the PHY IP inside your design, please set it as "0".
I try it in a simple design , I seeing the compilation passing, please have a try in rootport as well.
IF you seeing any new issue , please let me know the error code or any printscreen will do. We can solve this together.
Regards,
Wincent_Altera
