Forum Discussion
Occasional ContributorAgilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1
Good day,
I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the old EMIF IP with the HPS EMIF IP (emif_io96b_hps).
I can generate the HDL from Platform Designer without any errors. I get the following error when compiling:
Error(17821): Netlist error at hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd(275): port 's1_axi4_wuser' of width 64 cannot connect to actual of width 32
Details:
- Quartus 24.3.1 is used with all IP upgraded.
- I connect the io96b0_to_hps conduits of the HPS and HPS EMIF together.
- The channel 1 axi4 wuser is 32 bits wide for both the HPS and EMIF:
- I am using LPDDR4 with configuration of 2x16 (8Gbit).
- In hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd the wuser signals are all of width 32.
I am unable to see where the 64-bit wide signal is and how to fix it.
C:/Firmware/CheetahTacticalRouter/tactical-router-fw/tactical_router_fpga/quartus/ip/hps_system/hps_system_emif_io96b/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/synth/ip/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4/synth/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd
26 Replies
Jeet14Frequent Contributor
Hi,
Thanks Sstrell for helping on customer issue.
Looks like this issue is resolved now.
Regards
Tiwari
Nicole04This is the error I get when trying to generate the example design. It is not available.
Has the updated IP been tested?
- Nicole04
I realized that the error disappears when the EMIF (in HPS and EMIF IP parameter settings) is set to 1x32 instead of 2x16.
sstrellSuper Contributor
Your screenshot is for your PD system, not the IP itself. You have to go into the IP parameter editor for the EMIF and there is an Example Design tab for configuring the example design and a button in the upper right to generate the example design based on the parameter settings.
- sstrell
No, I mean a customized example design you generate from the IP Parameter Editor that creates a whole project for you based on the settings you specify in the Parameter Editor. This is a good way to create a complete design quickly.
- Nicole04
Yes, I understand, but there is no option for this.
Is there a different path from which this can be done?
- sstrell
It looks OK. Is this an example design you generated or a design you built yourself? Perhaps try generating the example design and then customize that as needed if you built this manually.
- Nicole04
Good day,
This is not an example design; no example design exists for this. The Quartus 24.2 design was based on the development kit and worked. This seems to be either an issue with the latest Quartus (24.3.1) or the updated IP Cores for this version.
If I remove the EMIF then it complains about other HPS pins, such as USB2 not being connected, however it is not something that is done outside of the IP core and the settings show it is connected. This is why I think there may be issues with the HPS IP.
- Nicole04
Good day,
Platform Designer Connections:
EMIF Parameters:
HPS Parameters:
I added the last two images for the HPS Parameters as attachments, because they did not want to load here.
The system compiled without errors in Quartus 24.2. I had to upgrade the HPS and EMIF IP, the remaining HPS related IP did not change.
Let me know if you require any further information.
- sstrell
Can you show your connections and parameter settings in PD?
