Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

Your screenshot is for your PD system, not the IP itself. You have to go into the IP parameter editor for the EMIF and there is an Example Design tab for configuring the example design and a button in the upper right to generate the example design based on the parameter settings.

https://www.intel.com/content/www/us/en/docs/programmable/817394/24-3-1/about-the-external-memory-interfaces-fpga-ip.html