Forum Discussion
After watchdog for dual-config is enabled, the FPGA seems like not work properly every dozens of seconds. Why?
FPGA communicates with another FPGA with PHY chip. Normally(watchdog enable checkbox not checked), the PHY link led is always off when communication is good. While after I enble watchdog for dual-config(watchdog enable checkbox checked) and set watchdog value to any value, the link led will be on for about 2 seconds and return to be off. This will also be repeated after dozens of seconds. Why? How will I use the watchdog for dual-config? I didn't run remote update after power-up and the FPGA just run application firmware(just ethernet communication with another FPGA using PHY chip).
Attached file is my fpga code for the dual-config.
54 Replies
- JohnT_Altera
Regular Contributor
Hi,
May I know how do you connect the On Chip Flash IP? Not sure if you are able to follow the connection in my attach design example on connecting the On Chip Flash IP to JTAG to Avalon Master? You may follow the guide in the document in order to run the System Console and update the UFM.
Please let me know if the document is not sufficient.
- JohnT_Altera
Regular Contributor
Hi,
May I know if you have On Chip Flash IP in your design?
The design example that I provide is for your to create a sof file which can use it to update the UFM flash using rpd or writing directly to the exact location. Recompilation is not needed once you created the sof file for you to modify the UFM memory anytime.
- KWang97
Occasional Contributor
Hi,@JohnT (Intel)
Thanks for your idea. While The problem is that workers in factory can’t compile. They just can program a file into FPGA.
They will edit a file with different serial number to each product and then program the file into FPGA.
Is there a method that I can edit a file and then directly program the file into FPGA without compiling. Thanks!
- JohnT_Altera
Regular Contributor
- JohnT_Altera
Regular Contributor
Hi,
You can create a simple JTAG to Avalon Master IP with On Chip Flash IP design to program to Max 10 device and use Quartus System Console to write into the specific UFM address to store the Serial Number.
Attach is the design example that I created for Max 10 Development kit.
- JohnT_Altera
Regular Contributor
Hi,
This is not possible if you are using POF file as it contain checksum for CRC checking.
May I know if you are able to update the UFM with the serial number after the POF is programmed? The reason is that I would recommend you to use JTAG Master and On Chip Flash IP to update the UFM with Serial Number so that it will be easier to be implemented.
- JohnT_Altera
Regular Contributor
Hi,
May I know if each device will have it's own serial number? The reason is that if you would like to implement different serial number for each pof file will be difficult.
If this is The case then I would recommend you to use On Chip Flash IP to directly program the bitstream using rpd file (raw programming file) then this will make you easier to modify the rpd file as it is a raw binary file and you may refer to .map file to determine where you can use to store the serial number. This will be more harder to implement as you need to create a design where you can update the UFM directly.