After watchdog for dual-config is enabled, the FPGA seems like not work properly every dozens of seconds. Why?

my fpga code for the dual-config.

Hi,

From the FPGA code, I do not observed that you performed watchdog timer reset. You will need to assert RU_nRSTIMER since you enable the watchdog timer. Please refer to table 34 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf in order to performed watchdog timer reset

At the end of the code, I reset watchdog together with set reconfig by assigning sl32avmm_rcv_writedata <= X"00000003"; Is this not right?

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000003";

Hi,

The write data X"00000003" will assert both trigger reconfiguration and reset the watchdog timer. The write data should be X"00000002" as this will set the bit 1 reset watchdog timer only.

Will i need to ​ reset watchdog timer frequently, or just at the time when I need reconfiguration?@JohnT_Intel​

Hi,

You just need to performed once after you reconfigure the Max 10 device.

Will the code below OK? But after write sl32avmm_rcv_writedata <= X"00000001"; then FPGA will be reconfiged, I guess FPGA will not receive reset cmd sl32avmm_rcv_writedata <= X"00000002"; How should I set reconfig and watchdog reset in my code? Thanks!@JohnT_Intel​

(50Mhz clock)

when ST_DUALCONFIG_TRIGGER =>

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

if sl32avmm_rcv_readdata(0) = '0' then

stDualConfigState <= ST_DUALCONFIG_TRIGGER_DONE;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000001";

end if;

when ST_DUALCONFIG_TRIGGER_DONE =>

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000002";

when others =>

null;

end case;

Hi,

It looks good but there is still some problem where the state machine will be reset whenever you trigger the reconfiguration. So I do not think that it will go to ST_DUALCONFIG_TRIGGER_DONE state. You will need to modify your code so that when the Application image is loaded then you will performed watchdog timer reset.

I modified my code like below. Is this OK? But PHY communication still not work normally. Once I disable the " watchdog enable checkbox" it's OK while after enable it, it will not be OK. I reset watchdog only once at the initial state highlighted with bold character.

DualConfig0 : process( plClk )

begin

if rising_edge( plClk ) then

slavmm_rcv_read <= '0';

sl3avmm_rcv_address <= B"000";

slavmm_rcv_write <= '0';

sl32avmm_rcv_writedata <= X"00000000";

case stDualConfigState is

when ST_DUALCONFIG_IDLE =>

if slGoReboot = '1' then

if slToBeErase = '0' then

stDualConfigState <= ST_DUALCONFIG_WRWAIT;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"001";

sl32avmm_rcv_writedata <= X"00000001"; -- application image(image0)

end if;

if slFaultRetrigger = '1' then

stDualConfigState <= ST_DUALCONFIG_WRWAIT;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"001";

sl32avmm_rcv_writedata <= X"00000003"; -- factory image(image1)

end if;

end if;

if slWatchdogResetFlg = '0' then

slWatchdogResetFlg <= '1';

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000002";

end if;

when ST_DUALCONFIG_WRWAIT =>

stDualConfigState <= ST_DUALCONFIG_READ;

when ST_DUALCONFIG_READ =>

stDualConfigState <= ST_DUALCONFIG_RDWAIT;

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

when ST_DUALCONFIG_RDWAIT =>

stDualConfigState <= ST_DUALCONFIG_TRIGGER;

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

when ST_DUALCONFIG_TRIGGER =>

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

if sl32avmm_rcv_readdata(0) = '0' then

stDualConfigState <= ST_DUALCONFIG_TRIGGER_DONE;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000001";

end if;

when ST_DUALCONFIG_TRIGGER_DONE =>

null;

when others =>

null;

end case;

end if;

end process;

@JohnT_Intel​