FPGA communicates with another FPGA with PHY chip. Normally(watchdog enable checkbox not checked), the PHY link led is always off when communication is good. While after I enble watchdog for dual-config(watchdog enable checkbox checked) and set watchdog value to any value, the link led will be on for about 2 seconds and return to be off. This will also be repeated after dozens of seconds. Why? How will I use the watchdog for dual-config? I didn't run remote update after power-up and the FPGA just run application firmware(just ethernet communication with another FPGA using PHY chip).Attached file is my fpga code for the dual-config.

my fpga code for the dual-config.

Hi,From the FPGA code, I do not observed that you performed watchdog timer reset. You will need to assert RU_nRSTIMER since you enable the watchdog timer. Please refer to table 34 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf in order to performed watchdog timer reset

At the end of the code, I reset watchdog together with set reconfig by assigning sl32avmm_rcv_writedata <= X"00000003"; Is this not right? slavmm_rcv_write <= '1'; sl3avmm_rcv_address <= B"000"; sl32avmm_rcv_writedata <= X"00000003";

Hi,The write data X"00000003" will assert both trigger reconfiguration and reset the watchdog timer. The write data should be X"00000002" as this will set the bit 1 reset watchdog timer only.

Will i need to reset watchdog timer frequently, or just at the time when I need reconfiguration?@JohnT_Intel

After watchdog for dual-config is enabled, the FPGA seems like not work properly every dozens of seconds. Why?

54 Replies

JohnT_Altera
Regular Contributor
6 years ago
Hi,
It is part of the Quartus software. In Quartus --> Tools --> System Debugging Tools --> System Console.
KWang97
Occasional Contributor
6 years ago
Is System Console Quartus software? How to open it. I don't know what it is.
JohnT_Altera
Regular Contributor
6 years ago
Hi,
Please open System Console and load the .tcl file provided. Then you can follow the userguide on how to use it. Just focus on using the ASMI parallel location as this is connected to On Chip Flash IP.
KWang97
Occasional Contributor
6 years ago
Hi,@JohnT (Intel)
Thanks for your explanation. While I am a newer on this, so could you please tell me detaily on how to use System Console to write it?
JohnT_Altera
Regular Contributor
6 years ago
Hi,
After connecting and follow the memory mapping in the Platform designer, then you can directly use System Console to write it.
KWang97
Occasional Contributor
6 years ago
After connecting the On Chip Flash IP to JTAG to Avalon Master, then what's the next step? How to code in FPGA and how to operate to realize the function that I can modify the generated file and then directly program into FPGA.
Then FPGA will have application image in CFM and serial number in UFM.
JohnT_Altera
Regular Contributor
6 years ago
Hi,
This is the connection. So when you generate the HDL code using Platform designer then it will generate the code for you.
The picture you are observing the overall connection where Platform Designer will show how the Avalon is connected.
KWang97
Occasional Contributor
6 years ago
I can only open file like this picture. But I can't see any other information like code to operate this qsys.
JohnT_Altera
Regular Contributor
6 years ago
Hi,
Please use Qsys or Platform Designer under Tools to open the system level design.
KWang97
Occasional Contributor
6 years ago
Hi,@JohnT (Intel)
I just use flash IP and instantiated in VHDL. I just write and read with VHDL and didn't use others connected with flash IP. So please give me more specific resources about this. The userguide.dox is very simple and I can't get anythin about it.
I also can just open the project you uploaded as pictures below, how to see the code ?