After watchdog for dual-config is enabled, the FPGA seems like not work properly every dozens of seconds. Why?

I modified my code like below. Is this OK? But PHY communication still not work normally. Once I disable the " watchdog enable checkbox" it's OK while after enable it, it will not be OK. I reset watchdog only once at the initial state highlighted with bold character.

DualConfig0 : process( plClk )

begin

if rising_edge( plClk ) then

slavmm_rcv_read <= '0';

sl3avmm_rcv_address <= B"000";

slavmm_rcv_write <= '0';

sl32avmm_rcv_writedata <= X"00000000";

case stDualConfigState is

when ST_DUALCONFIG_IDLE =>

if slGoReboot = '1' then

if slToBeErase = '0' then

stDualConfigState <= ST_DUALCONFIG_WRWAIT;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"001";

sl32avmm_rcv_writedata <= X"00000001"; -- application image(image0)

end if;

if slFaultRetrigger = '1' then

stDualConfigState <= ST_DUALCONFIG_WRWAIT;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"001";

sl32avmm_rcv_writedata <= X"00000003"; -- factory image(image1)

end if;

end if;

if slWatchdogResetFlg = '0' then

slWatchdogResetFlg <= '1';

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000002";

end if;

when ST_DUALCONFIG_WRWAIT =>

stDualConfigState <= ST_DUALCONFIG_READ;

when ST_DUALCONFIG_READ =>

stDualConfigState <= ST_DUALCONFIG_RDWAIT;

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

when ST_DUALCONFIG_RDWAIT =>

stDualConfigState <= ST_DUALCONFIG_TRIGGER;

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

when ST_DUALCONFIG_TRIGGER =>

slavmm_rcv_read <= '1';

sl3avmm_rcv_address <= B"011";

if sl32avmm_rcv_readdata(0) = '0' then

stDualConfigState <= ST_DUALCONFIG_TRIGGER_DONE;

slavmm_rcv_write <= '1';

sl3avmm_rcv_address <= B"000";

sl32avmm_rcv_writedata <= X"00000001";

end if;

when ST_DUALCONFIG_TRIGGER_DONE =>

null;

when others =>

null;

end case;

end if;

end process;