Forum Discussion
JohnT_Altera
Regular Contributor
6 years agoHi,
From the FPGA code, I do not observed that you performed watchdog timer reset. You will need to assert RU_nRSTIMER since you enable the watchdog timer. Please refer to table 34 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf in order to performed watchdog timer reset