New ContributorAfter PreSICE calibration ATX PLL doesn't lock
Hi all,
I'm currently trying to reconfigure the ATX PLL of an Arria 10 device to a different data rate via HPS reconfiguration interface.
The IP is configured and fitted for 2400 Mbps operation (1200 MHz) with a free-running reference clock of 80 MHz with very good signal integrity (from LMK04828).
In a second step I generate the whole interface for 3200 Mbps (1600 MHz) and extract the reconfiguration register values from the QSys generated design (C-Header file).
After this I follow the reconfiguration guide and write all values of the Header file to the interface.
I read these values back before and after PreSICE calibration and found, that the engine overwrites the internal voltage regulator settings (Register 0x102 should be 0xB5 and is 0x15, Register 0x11C should be 0x00 and is 0x20).
Furthermore the PLL doesn't emit the pll_locked signal (checked with SignalTap). When reconfiguring to a rate of 4800 the pll_locked signal turns high, but PreCISE also changes values here.
I'm currently doing the following steps for reconfiguration:
1. Apply reset to ResetSequencer IP
2. Aquire arbitration (Write 2 to Address 0)
3. Wait for Address 0x280[2] == 0
4. Reconfigure ATX PLL
5. Write 1 to 0x100 (activates PreSICE calibration)
6. Release Arbitration (Write 1 to Address 0)
7. Wait for calibration done (0x280[1] == 0)
8. Release ResetSequencer IP reset
Do you have an idea, why the PLL doesn't lock?
Many thanks for help in advance.
