New Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the A10 ATX PLL dynamic reconfiguration. You seems to observe that after reconfiguration, your ATX PLL does not achieve lock. To facilitate further debugging, just would like to check with you on the following:
1. As I understand it, the ATX PLL support embedded streamer and multi profile dynamic reconfiguration. Just wonder if you have a chance to try with it.
2. Just wonder if you have had a chance to run a Modelsim simulation to verify the functional behavior? If not, it is recommended for your to create a simple test design using embedded streamer and multi profile. Then run through the Modelsim simulation.
Please let me know if there is any concern. Thank you.
New ContributorHi @CheePin_C_Intel ,
sorry for answering this late.
The embedded Streamer isn't really an option, because I have lots of profiles I'd need to embedd.
I did a QuestaSim simulation though and found everything to work when reconfiguring the PLL manually.
There are some weird effects in the simulation though. I doublecheck all registervalues before and after PreCISE calibration and found, that all register values before calibration were as specified, while all registervalues after calibration changed (according to documentation are even incorrect (e.g. wrong counter values), even though the correct frequency appears). This doesn't happen in the real hardware, but then again the real hardware doesn't run correctly.
This leads me to the assumption, that maybe something with the CLKUSR is wrong. I set the "Device initialization clock source" to "CLKUSR Pin" in "Device and Pin Options" -> "General" and have a free-running 125 MHz clock connected to this pin. Do I need to take care of something additionally in HDL or assignment editor?
Edit: I found that in Arria V and Cyclone V channel bonding mode prohibits ATX PLL reconfiguration. While I didn't find the same in Arria 10 documentation I wonder if the ATX PLL behaves the same.
This is the registermap
| Address | Value pre calibraton | Value post calibration | Function |
| 0x103 | 0x21 | 0xbf | |
| 0x104 | 0x36 | 0x7f | |
| 0x105 | 0x05 | 0x47 | |
| 0x106 | 0x32 | 0x3f | |
| 0x107 | 0x00 | 0x3c | N Counter |
| 0x108 | 0x0b | 0x7f | L Counter |
| 0x109 | 0x50 | 0xff | M Counter |
| 0x10a | 0x04 | 0x7f | |
| 0x10b | 0x00 | 0xe1 | |
| 0x10c | 0x01 | 0xff | |
| 0x10d | 0x00 | 0xff | |
| 0x10e | 0x00 | 0xff | |
| 0x10f | 0x00 | 0xff | |
| 0x110 | 0x15 | 0x3d | |
| 0x111 | 0x00 | 0x70 | |
| 0x11a | 0x80 | 0xe0 | |
| 0x11b | 0x00 | 0xc0 | |
| 0x11c | 0x00 | 0xe0 | |
| 0x11d | 0x00 | 0xe0 | |
| 0x11f | 0x00 | 0x60 |
