After PreSICE calibration ATX PLL doesn't lock

Hi @CheePin_C_Intel ,

sorry for answering this late.

The embedded Streamer isn't really an option, because I have lots of profiles I'd need to embedd.
I did a QuestaSim simulation though and found everything to work when reconfiguring the PLL manually.

There are some weird effects in the simulation though. I doublecheck all registervalues before and after PreCISE calibration and found, that all register values before calibration were as specified, while all registervalues after calibration changed (according to documentation are even incorrect (e.g. wrong counter values), even though the correct frequency appears). This doesn't happen in the real hardware, but then again the real hardware doesn't run correctly.

This leads me to the assumption, that maybe something with the CLKUSR is wrong. I set the "Device initialization clock source" to "CLKUSR Pin" in "Device and Pin Options" -> "General" and have a free-running 125 MHz clock connected to this pin. Do I need to take care of something additionally in HDL or assignment editor?

Edit: I found that in Arria V and Cyclone V channel bonding mode prohibits ATX PLL reconfiguration. While I didn't find the same in Arria 10 documentation I wonder if the ATX PLL behaves the same.

This is the registermap