After PreSICE calibration ATX PLL doesn't lock

Hi,

Sorry for the delay. Please see my response as following:

This leads me to the assumption, that maybe something with the CLKUSR is wrong. I set the "Device initialization clock source" to "CLKUSR Pin" in "Device and Pin Options" -> "General" and have a free-running 125 MHz clock connected to this pin. Do I need to take care of something additionally in HDL or assignment editor?

[CP] For your information, I am not sure about using the CLKUSR as device initialization clock source. Based on my understanding, on the board, we just need to supply a free-running and stable clock with the supported frequency to the CLKUSR pin. We do not need to add any additional assignment or setting in Quartus.

To further narrow down to reconfiguration related or recalibration related, it is recommended for your to do the following:

1. Create a simple test design ie with one channel Native PHY

2. Enable the embedded streamer and multi profiles features in Native PHY

3. Perform the reconfiguration using embedded streamer

4. Then perform ATX PLL calibration using your current method

If using embedded streamer + profile, you are still seeing similar problem, then we could further narrow down to recalibration. If using embedded streamer + profile and there is no problem, then we could narrow down to the reconfiguration steps.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin