Accessing CRC_ERROR circuitry in user logic

There isn't a megawizard for the CRC configuration verification function. To access the CRC_ERROR function internally, you'll need to manually instantiate the <device>_crcblock primitive (cycloneiii_crcblock, for example). The verilog instance is in the app note, the VHDL component (for cyclone III) looks like this:

component cycloneiii_crcblock

generic (

lpm_type : string := "cycloneiii_crcblock" );

port(

clk : in std_logic := '0';

crcerror : out std_logic;

ldsrc : in std_logic := '0';

regout : out std_logic;

shiftnld : in std_logic := '0'

);

end component;

This one was found in the cycloneiii_components.vhd file in the ...\quartus\libraries\vhdl\wysiwyg directory in your installation directories.

Once you instantiate this in your code, connect the crc_error port to a bidirectional pin. You can then use the input function of that pin to access the CRC_ERROR signal in your design. I don't think Quartus will let you access CRC_ERROR any other way, since there's a dedicated path from the error detection logic to the I/O cell, so it had to pass through a bidir pin before being available in the FPGA fabric.

I hope that helps.

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I don't think Quartus will let you access CRC_ERROR any other way, since there's a dedicated path from the error detection logic to the I/O cell, so it had to pass through a bidir pin before being available in the FPGA fabric.

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Yes, see AN357. Also, according to the doc, there's no means to force a CRC error for test (apart from loading a configuration that has CRC error).

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There isn't a megawizard for the CRC configuration verification function. To access the CRC_ERROR function internally, you'll need to manually instantiate the <device>_crcblock primitive (cycloneiii_crcblock, for example). The verilog instance is in the app note, the VHDL component (for cyclone III) looks like this:

component cycloneiii_crcblock

generic (

lpm_type : string := "cycloneiii_crcblock" );

port(

clk : in std_logic := '0';

crcerror : out std_logic;

ldsrc : in std_logic := '0';

regout : out std_logic;

shiftnld : in std_logic := '0'

);

end component;

This one was found in the cycloneiii_components.vhd file in the ...\quartus\libraries\vhdl\wysiwyg directory in your installation directories.

Once you instantiate this in your code, connect the crc_error port to a bidirectional pin. You can then use the input function of that pin to access the CRC_ERROR signal in your design. I don't think Quartus will let you access CRC_ERROR any other way, since there's a dedicated path from the error detection logic to the I/O cell, so it had to pass through a bidir pin before being available in the FPGA fabric.

I hope that helps.

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Yes, this helps. Though I don't understand why this isn't directly documented by Altera.

Also, can I connect it to *any* bidir pin or only the crc_error out pin? If there's a dedicated path to a IO cell I'd guess I'm limited to the actual crc_error pin.

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Also, can I connect it to *any* bidir pin or only the crc_error out pin? If there's a dedicated path to a IO cell I'd guess I'm limited to the actual crc_error pin.

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You're going to have to use the CRC_ERROR pin, but once you bring it back into the fabric via the bidir, you can do whatever you want with it -- including routing it to another output pin.

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You're going to have to use the CRC_ERROR pin, but once you bring it back into the fabric via the bidir, you can do whatever you want with it -- including routing it to another output pin.

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Which is all a bit pointless really because if the FPGA does incur an SEU then that may well involve the pin routing CRAM - which in turn means the rerouted CRC_ERROR pin may well disappear on a CRC error!