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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

About JESD204b pin constrains

Hi:

I am using the Stratix 10 H-tile series FPGA, and for the JESD204B IP core, I found that in the example design, the voltage standard for rx data and refclk are constrained to CML. However, the refclk I am currently using is source from LMK00301, which cannot output a clock with CML standard. Can I constrain the data as CML, but constrain the clock as HCSL? Compile can passed.

Generic Io
  • ZH_Intel's avatar
    ZH_Intel
    2 years ago

    Hi Allen,

    Good day.

    Regarding to your question, yes LVDS and LVPECL will be better than HCSL.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel



7 Replies

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Thank you for reaching out.

    Apologize for the delayed response.

    Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

    I shall come back to you with findings.

    Thank you for your patience.

    Best Regards,

    ZH_Intel


  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Good day.

    Apologize for the delayed response.

    Based on the discussion with internal team, you may constrain the data as CML and constrain the clock as HCSL but it is not recommended by Intel as it will impact timing.

    By doing so will have risk.

    For JESD204 IP, it is advisable to connect direct Tx to Rx.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel


    • allen18's avatar
      allen18
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago
      Thank you for your reply.
      If I constrain the clock as lvds or lvpecl will be better than hcsl ?
  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Good day.

    Regarding to your question, yes LVDS and LVPECL will be better than HCSL.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel



  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Good day.

    Thank you for your respond on accepted solution.

    Do you still have further inquiries on this case?

    If there is no further inquiries, I will transition this thread to community support.

    Thank you.

    Best Regards,

    ZH_Intel



    • allen18's avatar
      allen18
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago
      Thank you,I plan to try to constrain the clock to LVDS and constrain the data to CML, no further inquiries
  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Thank you for your reply

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Stay safe, and I hope you have a great day.

    Thank you.

    Best Regards,

    ZH_Intel