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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

About JESD204b pin constrains

Hi: I am using the Stratix 10 H-tile series FPGA, and for the JESD204B IP core, I found that in the example design, the voltage standard for rx data and refclk are constrained to CML. However,...
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  • ZH_Intel's avatar
    ZH_Intel
    2 years ago

    Hi Allen,

    Good day.

    Regarding to your question, yes LVDS and LVPECL will be better than HCSL.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel



ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Allen,

Thank you for reaching out.

Apologize for the delayed response.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel