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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

About JESD204b pin constrains

Hi: I am using the Stratix 10 H-tile series FPGA, and for the JESD204B IP core, I found that in the example design, the voltage standard for rx data and refclk are constrained to CML. However,...
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  • ZH_Intel's avatar
    ZH_Intel
    2 years ago

    Hi Allen,

    Good day.

    Regarding to your question, yes LVDS and LVPECL will be better than HCSL.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel



ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Allen,

Good day.

Thank you for your respond on accepted solution.

Do you still have further inquiries on this case?

If there is no further inquiries, I will transition this thread to community support.

Thank you.

Best Regards,

ZH_Intel



  • allen18's avatar
    allen18
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago
    Thank you,I plan to try to constrain the clock to LVDS and constrain the data to CML, no further inquiries