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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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About JESD204b pin constrains

Hi: I am using the Stratix 10 H-tile series FPGA, and for the JESD204B IP core, I found that in the example design, the voltage standard for rx data and refclk are constrained to CML. However,...
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  • ZH_Intel's avatar
    ZH_Intel
    2 years ago

    Hi Allen,

    Good day.

    Regarding to your question, yes LVDS and LVPECL will be better than HCSL.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel



ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Allen,

Good day.

Apologize for the delayed response.

Based on the discussion with internal team, you may constrain the data as CML and constrain the clock as HCSL but it is not recommended by Intel as it will impact timing.

By doing so will have risk.

For JESD204 IP, it is advisable to connect direct Tx to Rx.

Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel


  • allen18's avatar
    allen18
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago
    Thank you for your reply.
    If I constrain the clock as lvds or lvpecl will be better than hcsl ?