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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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About JESD204b pin constrains

Hi: I am using the Stratix 10 H-tile series FPGA, and for the JESD204B IP core, I found that in the example design, the voltage standard for rx data and refclk are constrained to CML. However,...
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  • ZH_Intel's avatar
    ZH_Intel
    2 years ago

    Hi Allen,

    Good day.

    Regarding to your question, yes LVDS and LVPECL will be better than HCSL.

    Hope this answers your question.

    Thank you.

    Best Regards,

    ZH_Intel



ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Allen,

Thank you for your reply

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Stay safe, and I hope you have a great day.

Thank you.

Best Regards,

ZH_Intel