10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

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My next plan is to test board-to-board communication with the two boards rather than looping back on the same board using the provided TCL scripts. As I am new to such task and there are a lot to grasp, I wonder where I should start to realize my purpose.

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You can probably run exactly the same design on both boards, and just connect them together. Try it and see what happens. If nothing works, then read the Tcl scripts and see what they are doing.

Your current question is a little vague. Most people will not have your hardware setup, so cannot duplicate your system. So just start using the hardware and see how far you get. If you cannot understand what a particular SystemConsole Tcl sequence is doing, then you can ask specific questions, and you'll be more likely to get answers.

Cheers,

Dave

Thanks for your suggestions. Actually, I decide to use this example design because it provides not only the complete 10Gbps Ethernet subsystem but also the traffic controller and system controller so that I can simulate as well as test in hardware. And if I can use this for my boards and set up a board-to-board communication, I would only have to modify the MAC for my target application.

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You can probably run exactly the same design on both boards, and just connect them together. Try it and see what happens. If nothing works, then read the Tcl scripts and see what they are doing.

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I am trying to make some minor changes in Tcl scripts to disable the Loopback modes, and then try to test with local loopback (things happen on only one board with SMA connectors) first. If this works, I will then learn how to write a script for testing board-to-board mode.

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Your current question is a little vague. Most people will not have your hardware setup, so cannot duplicate your system.

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It seems like no one uses same setup as me, unfortunately.

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If you cannot understand what a particular SystemConsole Tcl sequence is doing, then you can ask specific questions, and you'll be more likely to get answers.

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I am learning Tcl scripting.

Thank you.

I modified the scripts and made it work with local loopback (using SMA cables in one board). I then created a script to work with board-to-board mode and only the transmitter works that gives statistics in System Console. But the receiver is not working. I cannot write to register and the error msg is as below:

error: This transaction did not complete in 60 seconds. System Console is giving up.

while executing

"master_write_32 {/devices/EP4S(100G2|40G2)@1#USB-0/(link)/JTAG/(110:132 v1# 0)/phy_0/master} {0x1000004} {0x00000001}"

while executing

"master_write_32 $port_id $address $wdata"

If you have any idea about the reason for this?

Thanks and wait for your suggestions.

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I cannot write to register

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If you have two boards connected to one PC, then you need to make sure SystemConsole only uses one board at a time. Look at the Tcl scripts and see how the scripts track whether the 'master' service is open.

With two boards, you need to open the 'master' service on the board, perform the read or write transaction, and then close the service. That way you can then read or write to the 'master' service on the other board.

Cheers,

Dave

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error: This transaction did not complete in 60 seconds. System Console is giving up.

while executing

"master_write_32 {/devices/EP4S(100G2|40G2)@1#USB-0/(link)/JTAG/(110:132 v1# 0)/phy_0/master} {0x1000004} {0x00000001}"

while executing

"master_write_32 $port_id $address $wdata"

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This error message indicates that SystemConsole did not get a response from the JTAG avalon master you are using.

First please rule out all the common failures - there should be no timing analysis failures from Quartus; the clock should be running and reset should not be held asserted.

Can you write to any other slaves using this master?

If so then the problem may be in the slave which you have at address 0x1000000 so that might be worth investigating.

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If you have two boards connected to one PC, then you need to make sure SystemConsole only uses one board at a time.

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I have two boards connected to two PCs running the same 'sof' file. I create one TCL script for the transmitter that generates burst of packets and sends out as well as collects relevant statistics and print out. Another script for the receiver is to collect statistics of data received. The statistics at transmitter look nice but the receiver does not work.

My understanding is that the scripts are used to access, read or/and write to a specific register of a component in the whole design. How are the register organized? are they inside the FPGA and randomly allocated? How does the author make sure that the register address and offsets assigned in the scripts match with the real address in the device?

Here is an example of assigning address and offset for Generator component (one avalon slave interface):

set GEN_BASE_ADDR 0x01000000

set GEN_START 0x0000000C

set GEN_STOP 0x00000010

Thank you.

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I have two boards connected to two PCs running the same 'sof' file. I create one TCL script for the transmitter that generates burst of packets and sends out as well as collects relevant statistics and print out. Another script for the receiver is to collect statistics of data received. The statistics at transmitter look nice but the receiver does not work.

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When you access each board, are you making sure to open the correct device? SystemConsole 'get service paths master' will return the path to both boards. Do you select one entry for the transmitter and the other for the receiver? How do you know which is which? Hint: in the system design, make the DIP switches readable, and set them differently on each board :)

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My understanding is that the scripts are used to access, read or/and write to a specific register of a component in the whole design. How are the register organized? are they inside the FPGA and randomly allocated?

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Since the system is being accessed using SystemConsole, its most likely implemented using SOPC Builder or Qsys. Open the system design with the appropriate tool and you will see the address map defined there.

If both boards have the same .sof, then they both have the same address map, and you need to make sure you access the transmitter board or receiver board as appropriate.

Cheers,

Dave

Thanks Dave for your quick answer.

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When you access each board, are you making sure to open the correct device? SystemConsole 'get service paths master' will return the path to both boards. Do you select one entry for the transmitter and the other for the receiver? How do you know which is which? Hint: in the system design, make the DIP switches readable, and set them differently on each board :)

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I am not sure if I fully understood your point. As I understand, System Console command "get_service_paths master" will return a list of master services connected to the host PC. And because I use two different PCs, each connected to a board separately. So, each System Console gets the path to each board, and I don't have to select service for transmitter and receiver after command "get_service_paths master". Am I wrong here?

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Since the system is being accessed using SystemConsole, its most likely implemented using SOPC Builder or Qsys. Open the system design with the appropriate tool and you will see the address map defined there.

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The design is composed of one Qsys based system (10Gbps MAC+ 10GBASE-R), one Traffic controller (in verilog) and one System controller (in verilog). I opened the Qsys system to see the base addresses of the MAC and the PHY but there are not. The base addresses should be assigned somewhere else. Usually, where people assign base address for a HDL-based component like Traffic controller?

Thanks

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because I use two different PCs, each connected to a board separately. So, each System Console gets the path to each board, and I don't have to select service for transmitter and receiver after command "get_service_paths master". Am I wrong here?

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With two separate PC hosts, each host will only see one USB-Blaster, so you're ok.

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I opened the Qsys system to see the base addresses of the MAC and the PHY but there are not. The base addresses should be assigned somewhere else. Usually, where people assign base address for a HDL-based component like Traffic controller?

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If the logic has registers, they should be accessible in Qsys. If the PHY is external and accessed via I2C (MDIO) then the Qsys memory map would contain an I2C controller. However, in the case of the Stratix IV GT, the MAC+PHY is all internal. If there is nothing in the Qsys memory map, then there are no registers implemented to control the ALTGX or ALTGX_RECONFIG components that the 10G logic is implemented on top of.

Cheers,

Dave

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If the logic has registers, they should be accessible in Qsys. If the PHY is external and accessed via I2C (MDIO) then the Qsys memory map would contain an I2C controller. However, in the case of the Stratix IV GT, the MAC+PHY is all internal. If there is nothing in the Qsys memory map, then there are no registers implemented to control the ALTGX or ALTGX_RECONFIG components that the 10G logic is implemented on top of.

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The 10G Ethernet is instantiated in top-level module. You can see the top module in the attachment. I think that I will need to study the design code and scripts more in order to make a board-to-board communication.

Thanks a lot.