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Altera_Forum
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13 years ago

10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

Hi all, I am trying to test board-to-board communication using a complete 10G Ethernet design that includes an Altera 10 GbE MAC + an Altera 10GBASE-R IP cores. My devices are Stratix IV GT and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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If the logic has registers, they should be accessible in Qsys. If the PHY is external and accessed via I2C (MDIO) then the Qsys memory map would contain an I2C controller. However, in the case of the Stratix IV GT, the MAC+PHY is all internal. If there is nothing in the Qsys memory map, then there are no registers implemented to control the ALTGX or ALTGX_RECONFIG components that the 10G logic is implemented on top of.

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The 10G Ethernet is instantiated in top-level module. You can see the top module in the attachment. I think that I will need to study the design code and scripts more in order to make a board-to-board communication.

Thanks a lot.