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Altera_Forum
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14 years ago

10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

Hi all, I am trying to test board-to-board communication using a complete 10G Ethernet design that includes an Altera 10 GbE MAC + an Altera 10GBASE-R IP cores. My devices are Stratix IV GT and...
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Altera_Forum
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14 years ago

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error: This transaction did not complete in 60 seconds. System Console is giving up.

while executing

"master_write_32 {/devices/EP4S(100G2|40G2)@1#USB-0/(link)/JTAG/(110:132 v1# 0)/phy_0/master} {0x1000004} {0x00000001}"

while executing

"master_write_32 $port_id $address $wdata"

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This error message indicates that SystemConsole did not get a response from the JTAG avalon master you are using.

First please rule out all the common failures - there should be no timing analysis failures from Quartus; the clock should be running and reset should not be held asserted.

Can you write to any other slaves using this master?

If so then the problem may be in the slave which you have at address 0x1000000 so that might be worth investigating.