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hongsy's avatar
hongsy
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2 years ago

100G interlaken usr_clk frequence cannot be modified

Hi ,

I use interlaken(2nd generation)Intel FPGA IP to gennerate a 12 lanes ,12.5G ,1 segment Interlaken IP.

The design example give a 300MHz to tx/rx_usr_clk.When I give a 311MHz pll clock to tx/rx_usr_clk, the Timing Analyzer has Setup and Hold problem.

I try to change rx/tx_clk's preriod in 2 files named altera_uflex_ilk_1921/synth/uflex_ilk_code_[ip_name]_altera_uflex_ilk_1921_[random num].sdc , but it dosen't soulve the timing problem.

My mother tongue is not Egnlish. So the expression may not accurately.

Thank you!

10 Replies

  • hongsy's avatar
    hongsy
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    2 years ago

    I checked doc of the Interlaken IP. It use 'recommended' 300Mhz, so I think usr_clk can be 311Mhz.

  • hongsy's avatar
    hongsy
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    2 years ago

    I must use version 19.4, becuase other modules have to be in 19.4. Thank you!

    • hongsy's avatar
      hongsy
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      2 years ago

      Hi Srie，

      Nice to meet you.

      It has not been solved yet.

      Thank you,

      Hong

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
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    2 years ago

    Hi Hong,


    Thanks for confirming. Based on your IP configuration, you're trying with 12 lanes with 12.5GBPS lane rate.

    The IP parameter editor prompts you to the recommended user clock frequency for the combination of number of lanes and data rates. The software derives the user clock frequency based on the configuration you select. The user clock frequency maps to the tx_usr_clk and rx_usr_clk signals.


    Based on UG, it's suggested to used 300MHz for ideal timing. Using any not recommended clock will trigger timing error. Is there any reason you're supplying 311MHz instead of 300MHz?


    Regards,

    Pavee


    • hongsy's avatar
      hongsy
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      2 years ago

      Hi,Paveetirra_Srie,

      Thank for your reply！

      It's better for using 311mhz. But if it can't be 311mhz, i can use 300mhz.

      Now i use 300mhz for testing, it still have timming warnning. The warnning is at clock ilkn_core_0|uflex_ilk_0|C2_xcvr|S10.xcvr_s10|tx_clkout|ch6 SLACK:-90.812 END Point TNS:-1179.112.

      I have done severial tests. I changed follow steps it will cause the same timming warning:

      1. support 311mhz clock by pin.

      2. support 300mhz clock by IOpll which i generate by IP Catalog.

      3. support 311mhz clock by IOpll which i generate by IP Catalog.

      4. support 300mhz clock by 'iopll' a module in ip's directory(module 'iopll' also instance in design example test_infra.sv) .

      I use 'iopll' and support other clock that ip needs as same as design example supprt.But it still has the same timming warning.I try to give reset synchronously, it still the same. I now don't have any idea to solve this problem. Do you have any suggestion?

      Dose this problem will lead to data be changed when transmitting?

      Hoping for you reply.

      Thank you!

      Hong

    • hongsy's avatar
      hongsy
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      2 years ago

      Hi Paveetirra_Srie,

      May be because I didn't port the constraints from example_design.sdc in desgin example. Now I am adding them in project, it solved the timing warning.

      Regards,

      Hong

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Hong,


    Right, you've to port the sdc into ED.

    Based on your last reply, you've mentioned that timing warning has been resolved. Any further support required on this issue?


    Regards,

    Pavee


  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
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    2 years ago

    Hi Hong,


    We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get the support from Intel experts.

    Otherwise, the community users will continue to help you on this thread.

    Thank you.