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hongsy's avatar
hongsy
Icon for New Contributor rankNew Contributor
2 years ago

100G interlaken usr_clk frequence cannot be modified

Hi , I use interlaken(2nd generation)Intel FPGA IP to gennerate a 12 lanes ,12.5G ,1 segment Interlaken IP. The design example give a 300MHz to tx/rx_usr_clk.When I give a 311MHz pll clock t...
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paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Hong,


Right, you've to port the sdc into ED.

Based on your last reply, you've mentioned that timing warning has been resolved. Any further support required on this issue?


Regards,

Pavee