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hongsy's avatar
hongsy
Icon for New Contributor rankNew Contributor
2 years ago

100G interlaken usr_clk frequence cannot be modified

Hi , I use interlaken(2nd generation)Intel FPGA IP to gennerate a 12 lanes ,12.5G ,1 segment Interlaken IP. The design example give a 300MHz to tx/rx_usr_clk.When I give a 311MHz pll clock t...
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paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Hong,


We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

Thank you.