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hongsy's avatar
hongsy
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2 years ago

100G interlaken usr_clk frequence cannot be modified

Hi , I use interlaken(2nd generation)Intel FPGA IP to gennerate a 12 lanes ,12.5G ,1 segment Interlaken IP. The design example give a 300MHz to tx/rx_usr_clk.When I give a 311MHz pll clock t...
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paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
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2 years ago

Hi Hong,


Good day to you.

Any update from my previous reply?


Regards,

Pavee


hongsy's avatar
hongsy
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2 years ago

Hi Paveetirra_Srie,

May be because I didn't port the constraints from example_design.sdc in desgin example. Now I am adding them in project, it solved the timing warning.

Regards,

Hong