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TKruse's avatar
TKruse
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Unable to interface the memory of custom peripheral correctly

Hello community,

I'm trying to write data to and read data from a custom ip via the HPS of a Cyclone V SoC. The custom ip is a simple RAM with 16 x 32 Bits of storage and connected via the LW AXI Bus as an avalon slave. (see qsys.png, component.png and memory_avalon.vhd)

When I write 32 bits into a register I would expect that only the addressed register is updated with the respective data but in my case writing to a register in the custom ip affects other registers, too. A few bits will be set depending on the input data in the other registers (see output.txt). Also strange is, that I cannot write to the

The system is created in the platform designer and the generated .qsys file is used as the top-level file. In the pin planner the clock and reset signals are assigned and the system synthesizes successfully. Then, I regenerated the preloader.

Afterwards, I use a uboot image and a linux kernel to boot into a terminal. In linux I wrote a simple user space application that mmaps the peripheral into ram (code is adjusted from the "Embedded Linux Beginners Guide" from Rocketboards.org) that can read and write those registers. (see testsystem.c)

In the BFM simulation the registers could be written and read correctly. Therefore, I think something is wrong with my linux configuration or my userspace application.

Has anybody faced such a problem yet ?

Since I'm new to this forum I hope that the provided information is sufficient. If not, please ask for specific parts.

Thanks in advance!
Tim

  • TKruse's avatar
    TKruse
    5 years ago

    Hello,

    thanks for your reply. The address is 0x0 or 0x3f I don't remember but it should be close to the lightweight bus base. But in the meanwhile I found the issue.

    The avalon read process that I implemented was not complete. The else part for the "if avs_s0_read = '1' then" was missing. Therefore, the syntheziser inferred this process to be registered and clocked by "avs_s0_read". The message about the incorrectly inferred registered process was hidden among the warnings.

    After implementing the else block and putting all read signals into the sensitivity list the peripheral works as expected. Although, I read in one of the threads in this community that the sensitivity list should not be the issue since it's not used during synthesizing but only for simulation.

6 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    It's a relatively simple design, so this is a strange failure. Is the compiled hardware design meeting timing in Quartus?

    If so, it might be worth it to add Signal Tap to the design to look at the signaling at the custom memory during writes and reads. The processor is performing spurious writes to other addresses that you're not accessing and the logic analyzer might help figure it out by seeing when those writes are occurring relative to when you expect them to occur.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Which Quartus version your are working on?

    My first suspicion would be is to check the preloader and U-boot compilation/generation. After you made changes in your qsys design, I presume you have re-generate the qsys file and re-compile the Quartus design.

    Are you using bsp-editor in the SoCEDS? Also, you may want to check if your BSEL, MSEL , CSEL pin have been set correctly.

  • TKruse's avatar
    TKruse
    Icon for New Contributor rankNew Contributor
    5 years ago

    @sstrell yes, the design is meeting the timing constraints. The system runs at 50MHz. I tried the SignalTap approach and only the addressed registers are written with the given value. (although bit 31 could not be written, which is strange, too).

    @EBERLAZARE_I_Intel I'm working with Quartus Prime Lite 18.1 (SoC EDS also 18.1). After changing anything in the Platform Designer I run a full compilation of the design (no errors) and rebuilt the preloader. I did not touch the u-boot image, since no project specific files are passed into u-boot for configuration. Same for the linux kernel. The used u-boot-socfpga (ACDS19.3_REL_GSRD_PR) and linux-socfpga (ACDS19.3_REL_GSRD_PR) configuration are working. Therefore, I just kept using them (maybe I'm wrong and I should rebuild them?). Finally, I created the mmc image with the "make_sdimage_p3.py" script from rocketboards and flashed the image into the emmc of the Cyclone V board/SoM I'm using.

    • EBERLAZARE_I_Intel's avatar
      EBERLAZARE_I_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi,

      Are you still facing this issue? May I know what is the base addresses of the slave that you are using in your platform designer that is connected to the AXI HPS master bridges?

      • TKruse's avatar
        TKruse
        Icon for New Contributor rankNew Contributor
        5 years ago

        Hello,

        thanks for your reply. The address is 0x0 or 0x3f I don't remember but it should be close to the lightweight bus base. But in the meanwhile I found the issue.

        The avalon read process that I implemented was not complete. The else part for the "if avs_s0_read = '1' then" was missing. Therefore, the syntheziser inferred this process to be registered and clocked by "avs_s0_read". The message about the incorrectly inferred registered process was hidden among the warnings.

        After implementing the else block and putting all read signals into the sensitivity list the peripheral works as expected. Although, I read in one of the threads in this community that the sensitivity list should not be the issue since it's not used during synthesizing but only for simulation.