Forum Discussion
New ContributorUnable to interface the memory of custom peripheral correctly
Hello,
thanks for your reply. The address is 0x0 or 0x3f I don't remember but it should be close to the lightweight bus base. But in the meanwhile I found the issue.
The avalon read process that I implemented was not complete. The else part for the "if avs_s0_read = '1' then" was missing. Therefore, the syntheziser inferred this process to be registered and clocked by "avs_s0_read". The message about the incorrectly inferred registered process was hidden among the warnings.
After implementing the else block and putting all read signals into the sensitivity list the peripheral works as expected. Although, I read in one of the threads in this community that the sensitivity list should not be the issue since it's not used during synthesizing but only for simulation.
New Contributor@sstrell yes, the design is meeting the timing constraints. The system runs at 50MHz. I tried the SignalTap approach and only the addressed registers are written with the given value. (although bit 31 could not be written, which is strange, too).
@EBERLAZARE_I_Intel I'm working with Quartus Prime Lite 18.1 (SoC EDS also 18.1). After changing anything in the Platform Designer I run a full compilation of the design (no errors) and rebuilt the preloader. I did not touch the u-boot image, since no project specific files are passed into u-boot for configuration. Same for the linux kernel. The used u-boot-socfpga (ACDS19.3_REL_GSRD_PR) and linux-socfpga (ACDS19.3_REL_GSRD_PR) configuration are working. Therefore, I just kept using them (maybe I'm wrong and I should rebuild them?). Finally, I created the mmc image with the "make_sdimage_p3.py" script from rocketboards and flashed the image into the emmc of the Cyclone V board/SoM I'm using.
EBERLAZARE_I_IntelRegular Contributor
Hi,
Are you still facing this issue? May I know what is the base addresses of the slave that you are using in your platform designer that is connected to the AXI HPS master bridges?
- TKruse
Hello,
thanks for your reply. The address is 0x0 or 0x3f I don't remember but it should be close to the lightweight bus base. But in the meanwhile I found the issue.
The avalon read process that I implemented was not complete. The else part for the "if avs_s0_read = '1' then" was missing. Therefore, the syntheziser inferred this process to be registered and clocked by "avs_s0_read". The message about the incorrectly inferred registered process was hidden among the warnings.
After implementing the else block and putting all read signals into the sensitivity list the peripheral works as expected. Although, I read in one of the threads in this community that the sensitivity list should not be the issue since it's not used during synthesizing but only for simulation.
