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TKruse's avatar
TKruse
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Unable to interface the memory of custom peripheral correctly

Hello community, I'm trying to write data to and read data from a custom ip via the HPS of a Cyclone V SoC. The custom ip is a simple RAM with 16 x 32 Bits of storage and connected via the LW AXI B...
  • TKruse's avatar
    TKruse
    5 years ago

    Hello,

    thanks for your reply. The address is 0x0 or 0x3f I don't remember but it should be close to the lightweight bus base. But in the meanwhile I found the issue.

    The avalon read process that I implemented was not complete. The else part for the "if avs_s0_read = '1' then" was missing. Therefore, the syntheziser inferred this process to be registered and clocked by "avs_s0_read". The message about the incorrectly inferred registered process was hidden among the warnings.

    After implementing the else block and putting all read signals into the sensitivity list the peripheral works as expected. Although, I read in one of the threads in this community that the sensitivity list should not be the issue since it's not used during synthesizing but only for simulation.

EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Which Quartus version your are working on?

My first suspicion would be is to check the preloader and U-boot compilation/generation. After you made changes in your qsys design, I presume you have re-generate the qsys file and re-compile the Quartus design.

Are you using bsp-editor in the SoCEDS? Also, you may want to check if your BSEL, MSEL , CSEL pin have been set correctly.

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