Stratix V IO pins in bank C & D cannot ramp to 3.3V when VCCIO is source with 3.3V

Hello,

Did you get any error message when trying to change the current strength settings?

Regards,

Aqid

i did not get any error message.

I would suggest you check the board if there is possible leakage short to the ground on those pins.

The 16mA current setting may override the leakage current that is why you can get 3.3v on the pins compared to 8mA and 12mA.

Stratix V : 5SGXMA3K3F40C4

Voltage and Current strength setting in .qsf file

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PINMAP_3C*
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PINMAP_3D*
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to PINMAP_3C*
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to PINMAP_3D*

VCCPD = 3.0V (Follow Stratix V spec from 2.85V to 3.15V)

VCCIO = 3.3V (Exceed Stratix V spec from 2.85V to 3.15V)

IO pins being measured are from bank/PINMAP_3C.

This pins are routed out from FPGA in the PCB but is not connected to a load. Means no possibility of board leakage since it is not connected to any load.

We are able to measured an expected 3.0V on the IO pins when VCCPD = 3.0V and VCCIO = 3.0V with current strength 8mA, 12mA & 16mA. This clearly prove that the PCB routing on the IO pins with no load has no leakage.

When we increase VCCIO = 3.3V while maintaining VCCPD = 3.0V, we saw an anomaly as follow :

8mA current strength : IO pins measured 1.25V (expect 3.3V)

12mA current strength : IO pins measured 1.56V (expect 3.3V)

16mA current strength : IO pins measured 3.29V

My Question is as follow:

1. You mention that 16mA current strength override the leakage protection circuit. Will the IO pins in this FPGA continue to function per normal?

2. Why did the 8mA and 12mA turn-on leakage protection circuit when the IO pins in Bank 3C is not connected to any load?

I think it may have something with the VCCPD as it is used to power the

I/O pre-drivers.

I checked the Pin Connection Guidelines for Stratix V; however, it is only mentioned on the 3.0V and not 3.3V.

The voltage on VCCPD is dependent on the VCCIO voltage.

When VCCIO is 3.0V, VCCPD must be 3.0V.

When VCCIO is 2.5V or less, VCCPD must be 2.5V

I am aware that the Pin Connection Guidelines for Stratix V stated that the recommended operating voltage 3.0V up to 3.15V and there is no mention of stratix V supporting 3.3V. One can argue that our design violated the recommended operating voltage, which may potential cause the IO pins (set at current strength of 8mA and 12 mA) unable to ramp up to 3.3V. But what puzzle me is that, why the IO pins behave differently when set at 16mA, where the IO pins is able to ramp to 3.3V.

I am also thinking, whether should i increase VCCPD from 3.0V to 3.3V, matching VCCPD to VCCIO at 3.3V. I wonder what will be the outcome?

I would suggest you to not trying something out of spec as it is not guaranteed for the performance and might damaging the device.

I can suggest you use lever shifter to convert signal to 3.3v as this is safer implementation. Lever shifter is an external component to convert signal voltage level.

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Behaviour beyond specified operation conditions is undefined and unlikely described in a document. I would first check if the device operates expectedly with legal VCCIO value. If not, the IO pin is either damaged or externally overloaded.