Stratix V IO pins in bank C & D cannot ramp to 3.3V when VCCIO is source with 3.3V

Stratix V : 5SGXMA3K3F40C4

Voltage and Current strength setting in .qsf file

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PINMAP_3C*
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PINMAP_3D*
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to PINMAP_3C*
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to PINMAP_3D*

VCCPD = 3.0V (Follow Stratix V spec from 2.85V to 3.15V)

VCCIO = 3.3V (Exceed Stratix V spec from 2.85V to 3.15V)

IO pins being measured are from bank/PINMAP_3C.

This pins are routed out from FPGA in the PCB but is not connected to a load. Means no possibility of board leakage since it is not connected to any load.

We are able to measured an expected 3.0V on the IO pins when VCCPD = 3.0V and VCCIO = 3.0V with current strength 8mA, 12mA & 16mA. This clearly prove that the PCB routing on the IO pins with no load has no leakage.

When we increase VCCIO = 3.3V while maintaining VCCPD = 3.0V, we saw an anomaly as follow :

8mA current strength : IO pins measured 1.25V (expect 3.3V)

12mA current strength : IO pins measured 1.56V (expect 3.3V)

16mA current strength : IO pins measured 3.29V

My Question is as follow:

1. You mention that 16mA current strength override the leakage protection circuit. Will the IO pins in this FPGA continue to function per normal?

2. Why did the 8mA and 12mA turn-on leakage protection circuit when the IO pins in Bank 3C is not connected to any load?