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jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Stratix V IO pins in bank C & D cannot ramp to 3.3V when VCCIO is source with 3.3V

Why is there difference in voltage level in bank 3C/3D IO pins when setting the current strength between 8mA, 12mA versus 16mA? I am expecting 3.3V on the IO pins but only get 1.5V when setting the c...
jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I am aware that the Pin Connection Guidelines for Stratix V stated that the recommended operating voltage 3.0V up to 3.15V and there is no mention of stratix V supporting 3.3V. One can argue that our design violated the recommended operating voltage, which may potential cause the IO pins (set at current strength of 8mA and 12 mA) unable to ramp up to 3.3V. But what puzzle me is that, why the IO pins behave differently when set at 16mA, where the IO pins is able to ramp to 3.3V.

I am also thinking, whether should i increase VCCPD from 3.0V to 3.3V, matching VCCPD to VCCIO at 3.3V. I wonder what will be the outcome?